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Multimode Reconfigurable Processing Unit (MM-RPU)
The Project
Power efficiency has become a top priority for the design of computing systems. The high power dissipation of computer installations renders operation and cooling increasingly expensive, especially for data centers. Moreover, the current efforts to save energy for protecting the global environment give this topic also an ecological dimension. In this project we want to make the case for using reconfigurable hardware technology to improve power efficiency for programmable computing systems.
The goal of the MM-RPU project is to investigate the architectural integration of reconfigurable processing units (RPUs) with classic microprocessor architectures, and to analyze and suggest corresponding programming environments. The innovative claim is that an RPU, which is controllable with low latency and equipped with an independent data feed, will improve the architecture’s power efficiency while preserving programmability.
Our Mission
We address two problems: architectural integration and programmability. We believe that advances in these areas will promote the proliferation of reconfigurable hardware technology in the general purpose computing domain.
The first problem concerns the architectural integration of CPU and RPU. It is not clear what the most efficient architectural coupling between RPU and CPU is. The CPU and the RPU operate on shared data that needs to be transferred (data access); further the CPU needs to control the operation of the RPU to synchronize the control flow (control access). These parameters span a two-dimensional design space. Closely related to the architectural coupling are the issues of system integration. When integrating the RPU into the microarchitecture we need to ensure that the system’s needs with regard to virtual memory, protection, and multi-process environments are not compromised.
The second and equally important problem is programmability. Currently, programming of reconfigurable fabrics mostly follows a hardware-centric approach. The RPU is specified with hardware description languages such as VHDL or Verilog, and synthesized using hardware tool-flows. A more programmer-friendly compilation-centric approach aims at generating the RPU implementation directly from C variants. Mostly, these C variants use only the syntax of C but impose a semantics resembling standard hardware description languages. While such hardware compilation techniques are emerging, we still need to evolve existing programming models into approaches that cover both the CPU and RPU. Compilation approaches extended by automated hardware/software partitioning might be a reasonable approach for RFUs, multi-threading programming models should be investigated for reconfigurable co-processors.
Funding and Collaboration
This project is funded by Intel Corporation and is conducted in cooperation with Intel Microprocessor Technology Lab (MTL) in Braunschweig, Germany.
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