PrintIMORC: An Infrastructure for Performance Monitoring and Optimization of Reconfigurable Computers
The Project
While research has demonstrated the potential of FPGAs as acceleration technology since decades, the creation of accelerators for realistic workloads has been hindered, at least partially, by the lack of commercially available systems. In the last years, however, computing system vendors began to offer machines that combine microprocessors with FPGAs. More recently, FPGA modules that fit into processor sockets have been introduced and provide a fairly standardized way of integrating hardware accelerators into mainstream computing systems.
Developing and optimizing accelerators for such machines is a challenge. Even if FPGA cores for important algorithmic kernels become more and more available, combining them into an overall accelerator remains tricky. Generally, the cores will show data-dependent runtimes and compete for shared resources such as external memory or the host interface, which makes it difficult to decide on a proper number of cores, their topology, the degree of core-level parallelism, data partitioning, etc.
Our Mission
To address these challenges, we have developed IMORC. IMORC is actually two things, an architectural template for creating core-based FPGA accelerators and an on-chip interconnect. The architectural template assists the designer in combining cores to an overall accelerator and greatly facilitates design space exploration, core reuse and portability. It assumes accelerators to be decomposed into a number of communicating cores. The IMORC interconnect relies on a flexible multi-bus structure with slave-side arbitration and offers FIFOs, bitwidth conversion and performance monitoring. The main design goals of IMORC include portability, ease of use and a high performance. For example, different kinds of memory can be transparently accessed by multiple cores without forcing the core to be modified depending on the memory's parameters. Especially performance monitoring is indispensable for debugging and optimizing FPGA accelerators.
Additionally to the communication infrastructure, IMORC provides a set of utility cores that facilitate the accelerator design. These utility cores implement functionalities often needed by different kinds of accelerators and thus decrease the development time for custom accelerators. Examples are job generation and decoding cores used for sending processing jobs from one core to another, farming cores for distributing workload between multiple cores and architecture support cores like memory controllers and host processor communication interfaces. With these features IMORC greatly simplifies the development of reconfigurable accelerators, as demonstrated in various case studies discussed in several publications.
