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Approximate Conjugate Gradient on FPGAs

In a nutshell

  • Implement Conjugate Gradient (CG) on an FPGA platform
  • Introduce timing-induced approximation
  • Evaluate gains in performance/energy consumption
  • Bonus: Explore scaling of approximation at runtime

Summary

Classic ways of increasing the performance of computing systems, raising the clock rate or increasing the number of transistors on a chip, are becoming increasingly challenging or already have come to an end. New ways of increasing speed or energy efficiency of applications are therefore needed. One promising new paradigm is Approximate Computing: trading in accuracy and reliability for efficiency.

An important computing problem is the solution of large systems of linear equations. An iterative method to find such solutions is the Conjugate Gradient (CG) method. It was shown that this method performs well for low precision arithmetic. [1]

The goal of this thesis is to implement the CG method on an FPGA platform using high-level synthesis tools and to introduce approximation into the data path. A particular interesting approximation technique on FPGAs is the overclocking of certain data paths in order to increase performance while sacrificing correct results. [2] This approximation technique should be the main focus of the work.

The developed implementation should finally be evaluated with regard to performance and energy efficiency. Dynamically scaling the level of approximation at runtime poses an additional interesting feature which can be evaluated as part of the thesis.

We provide

  • State-of-the-art FPGA technology from Xilinx and Altera
  • A high performance computing platform based on IBM POWER8

You should bring

  • Basic knowledge about FPGAs
  • Programming experience with C / OpenCL
  • Interest in unconventional computing paradigms

References

[1]: Klavik, P.; Malossi, A. C. I.; Bekas, C. & Curioni, A. Changing Computing Paradigms Towards Power Efficiency

[2]: Shi, K.; Boland, D. & Constantinides, G. A. Accuracy-Performance Tradeoffs on an FPGA through Overclocking

Contact

Michael Laß

Paderborn Center for Parallel Computing (PC2)

Research Associate

Michael Laß
Phone:
+49 5251 60-1722
Fax:
+49 5251 60-1714
Office:
O2.149
Web:

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