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Journal Papers

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A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices

D. Richters, M. Lass, A. Walther, C. Plessl, T. Kühne, Communications in Computational Physics (2019), pp. 564-585

We address the general mathematical problem of computing the inverse p-th root of a given matrix in an efficient way. A new method to construct iteration functions that allow calculating arbitrary p-th roots and their inverses of symmetric positive definite matrices is presented. We show that the order of convergence is at least quadratic and that adaptively adjusting a parameter q always leads to an even faster convergence. In this way, a better performance than with previously known iteration schemes is achieved. The efficiency of the iterative functions is demonstrated for various matrices with different densities, condition numbers and spectral radii.


Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots

M. Lass, T. Kühne, C. Plessl, Embedded Systems Letters (2018), pp. 33-36

Approximate computing has shown to provide new ways to improve performance and power consumption of error-resilient applications. While many of these applications can be found in image processing, data classification or machine learning, we demonstrate its suitability to a problem from scientific computing. Utilizing the self-correcting behavior of iterative algorithms, we show that approximate computing can be applied to the calculation of inverse matrix p-th roots which are required in many applications in scientific computing. Results show great opportunities to reduce the computational effort and bandwidth required for the execution of the discussed algorithm, especially when targeting special accelerator hardware.


Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs

H. Riebler, M. Lass, R. Mittendorf, T. Löcke, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems (TRETS) (2017), pp. 24:1-24:23

Branch and bound (B&B) algorithms structure the search space as a tree and eliminate infeasible solutions early by pruning subtrees that cannot lead to a valid or optimal solution. Custom hardware designs significantly accelerate the execution of these algorithms. In this article, we demonstrate a high-performance B&B implementation on FPGAs. First, we identify general elements of B&B algorithms and describe their implementation as a finite state machine. Then, we introduce workers that autonomously cooperate using work stealing to allow parallel execution and full utilization of the target FPGA. Finally, we explore advantages of instance-specific designs that target a specific problem instance to improve performance. We evaluate our concepts by applying them to a branch and bound problem, the reconstruction of corrupted AES keys obtained from cold-boot attacks. The evaluation shows that our work stealing approach is scalable with the available resources and provides speedups proportional to the number of workers. Instance-specific designs allow us to achieve an overall speedup of 47 × compared to the fastest implementation of AES key reconstruction so far. Finally, we demonstrate how instance-specific designs can be generated just-in-time such that the provided speedups outweigh the additional time required for design synthesis.

High-Throughput and Low-Latency Network Communication with NetIO

J. Schumacher, C. Plessl, W. Vandelli, Journal of Physics: Conference Series (2017)



Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code

G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, Computers and Electrical Engineering (2016), pp. 91-111

A broad spectrum of applications can be accelerated by offloading computation intensive parts to reconfigurable hardware. However, to achieve speedups, the number of loop it- erations (trip count) needs to be sufficiently large to amortize offloading overheads. Trip counts are frequently not known at compile time, but only at runtime just before entering a loop. Therefore, we propose to generate code for both the CPU and the coprocessor, and defer the offloading decision to the application runtime. We demonstrate how a toolflow, based on the LLVM compiler framework, can automatically embed dynamic offloading de- cisions into the application code. We perform in-depth static and dynamic analysis of pop- ular benchmarks, which confirm the general potential of such an approach. We also pro- pose to optimize the offloading process by decoupling the runtime decision from the loop execution (decision slack). The feasibility of our approach is demonstrated by a toolflow that automatically identifies suitable data-parallel loops and generates code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow with representative loops executed for different input data sizes.


Aktuelles Schlagwort: Approximate Computing

C. Plessl, M. Platzner, P.J. Schreier, Informatik Spektrum (2015), pp. 396-399


Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study

T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable Computing (IJRC) (2015)

FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x.

FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades

J. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. Schreuder, J. Schumacher, W. Vandelli, J. Vermeulen, J. Zhang, Journal of Physics: Conference Series (2015)

The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented and hardware and software aspects will be discussed.

Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction

S. Peitz, M. Dellnitz, PAMM (2015), pp. 613-614

In this article an efficient numerical method to solve multiobjective optimization problems for fluid flow governed by the Navier Stokes equations is presented. In order to decrease the computational effort, a reduced order model is introduced using Proper Orthogonal Decomposition and a corresponding Galerkin Projection. A global, derivative free multiobjective optimization algorithm is applied to compute the Pareto set (i.e. the set of optimal compromises) for the concurrent objectives minimization of flow field fluctuations and control cost. The method is illustrated for a 2D flow around a cylinder at Re = 100.

Self-Aware and Self-Expressive Systems – Guest Editor's Introduction

J. Torresen, C. Plessl, X. Yao, IEEE Computer (2015), pp. 18-20


Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung

S. Hegler, C. Statz, M. Mütze, H. Mooshofer, M. Goldammer, K. Fendt, S. Schwarzer, K. Feldhoff, M. Flehmig, U. Markwardt, W. E. Nagel, M. Schütte, A. Walther, M. Meinel, A. Basermann, D. Plettemeier, tm - Technisches Messen (2015), pp. 440-450

Große zylindrische Stahlprüflinge werden mittels der Methode der finiten Differenzen im Zeitbereich (engl. finite differences in time domain, FDTD) simulativ untersucht. Dabei werden Pitch-Catch-Messanordnungen verwendet. Es werden zwei Bildgebungsansätze vorgestellt: ersterer basiert auf dem Imaging Principle nach Claerbout, letzterer basiert auf gradientenbasierter Optimierung eines Zielfunktionals.


Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers

H. Giefers, C. Plessl, J. Förstner, ACM SIGARCH Computer Architecture News (2014), pp. 65-70


ReconOS - An Operating System Approach for Reconfigurable Computing

A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl, IEEE Micro (2014), pp. 60-71

The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications

Self-awareness as a Model for Designing and Operating Heterogeneous Multicores

A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (TRETS) (2014)

Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems.

Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators

A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and Microsystems (2014), pp. 911-919

Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.


Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices

S. Kasap, S. Redif, IEEE Trans. on Very Large Scale Integration (VLSI) Systems (2013), pp. 522-536



A Single Sign-On Infrastructure for Science Gateways on a Use Case for Structural Bioinformatics

S. Gesing, R. Grunzke, J. Krüger, G. Birkenheuer, M. Wewior, P. Schäfer, B. Schuller, J. Schuster, S. Herres-Pawlis, S. Breuers, Balaskó, M. Kozlovszky, A. Szikszay Fabri, L. Packschies, P. Kacsuk, D. Blunk, T. Steinke, A. Brinkmann, G. Fels, R. Müller-Pfefferkorn, R. Jäkel, O. Kohlbacher, Journal of Grid Computing (2012), pp. 769-790


Cost-aware and SLO Fulfilling Software as a Service

O. Niehörster, J. Simon, A. Brinkmann, A. Keller, J. Krüger, Journal of Grid Computing (2012), pp. 553-577

Virtualization technology makes data centers more dynamic and easier to administrate. Today, cloud providers offer customers access to complex applications running on virtualized hardware. Nevertheless, big virtualized data centers become stochastic environments and the simplification on the user side leads to many challenges for the provider. He has to find cost-efficient configurations and has to deal with dynamic environments to ensure service level objectives (SLOs). We introduce a software solution that reduces the degree of human intervention to manage clouds. It is designed as a multi-agent system (MAS) and placed on top of the Infrastructure as a Service (IaaS) layer. Worker agents allocate resources, configure applications, check the feasibility of requests, and generate cost estimates. They are equipped with application specific knowledge allowing it to estimate the type and number of necessary resources. During runtime, a worker agent monitors the job and adapts its resources to ensure the specified quality of service—even in noisy clouds where the job instances are influenced by other jobs. They interact with a scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low costs. The whole architecture is self-optimizing and able to use public or private clouds. Building a private cloud needs to face the challenge to find a mapping of virtual machines (VMs) to hosts. We present a rule-based mapping algorithm for VMs. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. An energy-aware scheduler and the availability of cheap resources provided by a spot market are analyzed. We evaluated our approach by building up an SaaS stack, which assigns resources in consideration of an energy function and that ensures SLOs of two different applications, a brokerage system and a high-performance computing software. Experiments were done on a real cloud system and by simulations.

IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators

T. Schumacher, C. Plessl, M. Platzner, Microprocessors and Microsystems (2012), pp. 110-126


On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors

M. Grad, C. Plessl, Int. Journal of Reconfigurable Computing (IJRC) (2012)


Parallel algorithm for computation of second-order sequential best rotations

S. Redif, S. Kasap, Int. Journal of Electronics (2012), pp. 1646-1651


Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer

S. Kasap, K. Benkrid, Journal of Computers (2012), pp. 1312-1328

Programming models for reconfigurable heterogeneous multi-cores

C. Plessl, M. Platzner, A. Agne, M. Happe, E. Lübbers, Self-Awareness in Autonomic Systems (2012)


STIR: Software for Tomographic Image Reconstruction Release 2

K. Thielemans, C. Tsoumpas, S. Mustafovic, T. Beisel, P. Aguiar, N. Dikaios, M. W Jacobson, Physics in Medicine and Biology (2012), pp. 867-883


Workflow-enhanced conformational analysis of guanidine zinc complexes via a science gateway

S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, S. Gesing, R. Grunzke, R. Jäkel, O. Kohlbacher, J. Krüger, I. Dos Santos Vieira, Studies in Health Technology and Informatics (2012), pp. 142-151



FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study

T. Schumacher, T. Süß, C. Plessl, M. Platzner, Int. Journal of Recon- figurable Computing (IJRC) (2011)


Infrastructure Federation Through Virtualized Delegation of Resources and Services

G. Birkenheuer, A. Brinkmann, M. Högqvist, A. Papaspyrou, B. Schott, D. Sommerfeld, W. Ziegler, Journal of Grid Computing (2011), pp. 355-377


Virtualized HPC: a contradiction in terms?

G. Birkenheuer, A. Brinkmann, J. Kaiser, A. Keller, M. Keller, C. Kleineweber, C. Konersmann, O. Niehörster, T. Schäfer, J. Simon, M. Wilhelm, Software: Practice and Experience (2011)

System virtualization has become the enabling technology to manage the increasing number of different applications inside data centers. The abstraction from the underlying hardware and the provision of multiple virtual machines (VM) on a single physical server have led to a consolidation and more efficient usage of physical servers. The abstraction from the hardware also eases the provision of applications on different data centers, as applied in several cloud computing environments. In this case, the application need not adapt to the environment of the cloud computing provider, but can travel around with its own VM image, including its own operating system and libraries. System virtualization and cloud computing could also be very attractive in the context of high‐performance computing (HPC). Today, HPC centers have to cope with both, the management of the infrastructure and also the applications. Virtualization technology would enable these centers to focus on the infrastructure, while the users, collaborating inside their virtual organizations (VOs), would be able to provide the software. Nevertheless, there seems to be a contradiction between HPC and cloud computing, as there are very few successful approaches to virtualize HPC centers. This work discusses the underlying reasons, including the management and performance, and presents solutions to overcome the contradiction, including a set of new libraries. The viability of the presented approach is shown based on evaluating a selected parallel, scientific application in a virtualized HPC environment.


Risikomanagement für verteilte Umgebungen

A. Brinkmann, D. Battré, G. Birkenheuer, O. Kao, K. Voß, ForschungsForum Paderborn (2010)


A Microdriver Architecture for Error Correcting Codes inside the Linux Kernel

A. Brinkmann, D. Eschweiler, Journal of Supercomputing (2009), pp. 35:1-35:10



Reformulating XPath queries and XSLT queries on XSLT views

S. Groppe, S. Böttcher, G. Birkenheuer, A. Höing, Data & Knowledge Engineering (2006), pp. 64-110



Anatomy of a Resource Management System for HPC Clusters

A. Keller, A. Reinefeld, Annual Review of Scalable Computing (2001), pp. 1-31

Workstation clusters are often not only used for high-throughput computing in time-sharing mode but also for running complex parallel jobs in space-sharing mode. This poses several difficulties to the resource management system, which must be able to reserve computing resources for exclusive use and also to determine an optimal process mapping for a given system topology. On the basis of our CCS software, we describe the anatomy of a modern resource management system. Like Codine, Condor, and LSF, CCS provides mechanisms for the user-friendly system access and management of clusters. But unlike them, CCS is targeted at the effective support of space-sharing parallel computers and even metacomputers. Among other features, CCS provides a versatile resource description facility, topology-based process mapping, pluggable schedulers, and hooks to metacomputer management.


Managing Clusters of Geographically Distributed High-Performance Computers

M. Brune, J. Gehring, A. Keller, A. Reinefeld, Concurrency, Practice, and Experience (1999), pp. 887-911

We present a software system for the management of geographically distributed high‐performance computers. It consists of three components: 1. The Computing Center Software (CCS) is a vendor‐independent resource management software for local HPC systems. It controls the mapping and scheduling of interactive and batch jobs on massively parallel systems; 2. The Resource and Service Description (RSD) is used by CCS for specifying and mapping hardware and software components of (meta‐)computing environments. It has a graphical user interface, a textual representation and an object‐oriented API; 3. The Service Coordination Layer (SCL) co‐ordinates the co‐operative use of resources in autonomous computing sites. It negotiates between the applications' requirements and the available system services.


Specifying Resources and Services in Metacomputing Environments

M. Brune, J. Gehring, A. Keller, B. Monien, Parallel Computing (1998), pp. 1751-1776

With a steadily increasing number of services, metacomputing is now gaining importance in science and industry. Virtual organizations, autonomous agents, mobile computing services, and high-performance client–server applications are among the many examples of metacomputing services. For all of them, resource description plays a major role in organizing access, use, and administration of the computing components and software services. We present a generic Resource and Service Description (RSD) for specifying the hardware and software components of (meta-) computing environments. Its graphical interface allows metacomputer users to specify their resource requests. Its textual counterpart gives service providers the necessary flexibility to specify topology and properties of the available system and software resources. Finally, its internal object-oriented representation is used to link different resource management systems and service tools. With these three representations, our generic RSD approach is a key component for building metacomputer environments.

The Latency-of-Data-Access model for Analyzing Parallel Computation

J. Simon, J. Wierum, Information Processing Letters - Special Issue on Models of Computation (1998), pp. 255-261


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