DATE2019 Tutorial on OpenCL design flows for Intel and Xilinx FPGAs

On March 25 2019, Tobias Kenter conducted a tutorial at the DATE 2019 conference in Florence under the title OpenCL design flows for Intel and Xilinx FPGAs - common optimization strategies, design patterns and vendor-specific differences. Featuring tools for both Intel and Xilinx FPGAs, this tutorial provides the community with practical guidance based on the experience in OpenCL based FPGA acceleration at PC².


An increasing fraction of new results in the reconfigurable computing domain are obtained with the help of high level synthesis tools. Among the more popular tools are the OpenCL based Xilinx SDAccel and Intel FPGA SDK for OpenCL. Since they are building upon the same programming model and source language, one would hope for portability between different OpenCL based FPGA designs. However, the vast majority of published research is only optimized for one vendor tool and FPGA family. In their dissemination and training activities, both vendors focus on promoting effective design patterns with their respective tools and for their respective hardware.

In this tutorial, we want to broaden that scope and provide training for both tool chains. During two years of PostDoc research, the workshop organizer has gained extensive experience and insights into these tools. This tutorial will contain step by step optimization examples with performance models based on analysis of generated reports and complemented with measurements and profiling data. We will present design patterns that work well for both tools and thus can promote portability of OpenCL based FPGA designs, but also shed light on differences. Based on examples, we will illustrate the central difference in pipelining of nested loops, which has implications on local memory ports, replication and predictability of design space exploration.


  • The main tutorial slides are available here. Tutorial participants have received additional material on the case studies that have been discussed selectively.
  • Design examples and generated compiler outputs are published in the accompanying github repository:

Dr. Tobias Kenter

Paderborn Center for Parallel Computing (PC2)

Fachberater FPGA Beschleunigung

E-Mail schreiben +49 5251 60-4340