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Data Center Building O

PerficienCC - Performance and Efficiency in HPC with Custom Computing

DFG Project in call "Performance Engineering für wissenschaftliche Software"

Numerous research projects have demonstrated that accelerators like field-programmable gate arrays (FPGAs), many-cores and graphics processing units (GPUs) can achieve substantial performance and energy-efficiency benefits for high-performance computing. Still, accelerators are not pervasively used so far – even for applications that could very likely profit from accelerators. There are numerous reasons for the reluctance of HPC developers to adopt accelerators, such as: lack of technical knowledge; unclear benefit of the time invested for porting and optimization; lack of an estimate of the acceleration potential; poor quality of materials that teach the use of accelerators; few libraries that allow a black-box use of accelerators.

In this project, we are establishing a structured support and consulting process in our HPC center that supports HPC developers during the complete process from performance analysis and estimation of the acceleration potential up to the optimization of the runtime-critical parts of their applications. This process infuses a complementary expertise into teams of developers from computational sciences and thus improves the cost/benefit ratio of code porting and optimization. Thus ultimately allows these scientists to reduce the program runtime or to simulate larger or more complex systems.

To allow developers to profit from previous work we will translate frequently used functions into reusable libraries. Finally, we will develop teaching materials that are tailored to the needs of computational scientists and collect code examples that illustrate best practices.

We will focus the work in this project on the technological and application-related or method-related competencies of our compute center and its users. As research of our main users work is concentrated in three main domains (nanophotonics, molecular dynamics and quantum chemistry) we can reuse domain-specific methods and experiences for different codes. Technologically, we will focus on FPGAs as accelerator technology, because FPGAs have the highest potential to improve the energy efficiency of computation and the market for FPGAs is currently thriving. We see a fertile basis for our research and development efforts, driven by first initiatives to standardize software stacks for FPGAs, the beginning of hardware integration of FPGA technologies in processors, the introduction of CAPI as a general accelerator interface by IBM and the increased maturity of FPGA development tools. We expect that our substantial expertise in custom computing with FPGAs and our focus on few application domains provide ideal conditions to make a significant progress in the application of FPGAs in HPC and allow for demonstrating and quantifying the potential to improve the performance and energy efficiency with real HPC codes.

Funding agencyDeutsche Forschungsgemeinschaft (DFG)
Funding identifierPL 595/2-1


Open list in Research Information System


A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K

M. Lass, R. Schade, T. Kühne, C. Plessl, in: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer Society, 2020, pp. 1127-1140

Electronic structure calculations based on density-functional theory (DFT) represent a significant part of today's HPC workloads and pose high demands on high-performance computing resources. To perform these quantum-mechanical DFT calculations on complex large-scale systems, so-called linear scaling methods instead of conventional cubic scaling methods are required. In this work, we take up the idea of the submatrix method and apply it to the DFT computations in the software package CP2K. For that purpose, we transform the underlying numeric operations on distributed, large, sparse matrices into computations on local, much smaller and nearly dense matrices. This allows us to exploit the full floating-point performance of modern CPUs and to make use of dedicated accelerator hardware, where performance has been limited by memory bandwidth before. We demonstrate both functionality and performance of our implementation and show how it can be accelerated with GPUs and FPGAs.

Accurate Sampling with Noisy Forces from Approximate Computing

V. Rengaraj, M. Lass, C. Plessl, T. Kühne, Computation (2020), 8(2), 39

In scientific computing, the acceleration of atomistic computer simulations by means of custom hardware is finding ever-growing application. A major limitation, however, is that the high efficiency in terms of performance and low power consumption entails the massive usage of low precision computing units. Here, based on the approximate computing paradigm, we present an algorithmic method to compensate for numerical inaccuracies due to low accuracy arithmetic operations rigorously, yet still obtaining exact expectation values using a properly modified Langevin-type equation.

CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations

T. Kühne, M. Iannuzzi, M.D. Ben, V.V. Rybkin, P. Seewald, F. Stein, T. Laino, R.Z. Khaliullin, O. Schütt, F. Schiffmann, D. Golze, J. Wilhelm, S. Chulkov, M.H.B. Mohammad Hossein Bani-Hashemian, V. Weber, U. Borstnik, M. Taillefumier, A.S. Jakobovits, A. Lazzaro, H. Pabst, T. Müller, R. Schade, M. Guidon, S. Andermatt, N. Holmberg, G.K. Schenter, A. Hehn, A. Bussy, F. Belleflamme, G. Tabacchi, A. Glöß, M. Lass, I. Bethune, C.J. Mundy, C. Plessl, M. Watkins, J. VandeVondele, M. Krack, J. Hutter, The Journal of Chemical Physics (2020), 152(19), 194103

CP2K is an open source electronic structure and molecular dynamics software package to perform atomistic simulations of solid-state, liquid, molecular, and biological systems. It is especially aimed at massively parallel and linear-scaling electronic structure methods and state-of-theart ab initio molecular dynamics simulations. Excellent performance for electronic structure calculations is achieved using novel algorithms implemented for modern high-performance computing systems. This review revisits the main capabilities of CP2K to perform efficient and accurate electronic structure simulations. The emphasis is put on density functional theory and multiple post–Hartree–Fock methods using the Gaussian and plane wave approach and its augmented all-electron extension.


A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices

D. Richters, M. Lass, A. Walther, C. Plessl, T. Kühne, Communications in Computational Physics (2019), 25(2), pp. 564-585

We address the general mathematical problem of computing the inverse p-th root of a given matrix in an efficient way. A new method to construct iteration functions that allow calculating arbitrary p-th roots and their inverses of symmetric positive definite matrices is presented. We show that the order of convergence is at least quadratic and that adaptively adjusting a parameter q always leads to an even faster convergence. In this way, a better performance than with previously known iteration schemes is achieved. The efficiency of the iterative functions is demonstrated for various matrices with different densities, condition numbers and spectral radii.

OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs

P. Gorlani, T. Kenter, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2019

Stratix 10 FPGA cards have a good potential for the acceleration of HPC workloads since the Stratix 10 product line introduces devices with a large number of DSP and memory blocks. The high level synthesis of OpenCL codes can play a fundamental role for FPGAs in HPC, because it allows to implement different designs with lower development effort compared to hand optimized HDL. However, Stratix 10 cards are still hard to fully exploit using the Intel FPGA SDK for OpenCL. The implementation of designs with thousands of concurrent arithmetic operations often suffers from place and route problems that limit the maximum frequency or entirely prevent a successful synthesis. In order to overcome these issues for the implementation of the matrix multiplication, we formulate Cannon's matrix multiplication algorithm with regard to its efficient synthesis within the FPGA logic. We obtain a two-level block algorithm, where the lower level sub-matrices are multiplied using our Cannon's algorithm implementation. Following this design approach with multiple compute units, we are able to get maximum frequencies close to and above 300 MHz with high utilization of DSP and memory blocks. This allows for performance results above 1 TeraFLOPS.


A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices

M. Lass, S. Mohr, H. Wiebeler, T. Kühne, C. Plessl, in: Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, 2018

We present the submatrix method, a highly parallelizable method for the approximate calculation of inverse p-th roots of large sparse symmetric matrices which are required in different scientific applications. Following the idea of Approximate Computing, we allow imprecision in the final result in order to utilize the sparsity of the input matrix and to allow massively parallel execution. For an n x n matrix, the proposed algorithm allows to distribute the calculations over n nodes with only little communication overhead. The result matrix exhibits the same sparsity pattern as the input matrix, allowing for efficient reuse of allocated data structures. We evaluate the algorithm with respect to the error that it introduces into calculated results, as well as its performance and scalability. We demonstrate that the error is relatively limited for well-conditioned matrices and that results are still valuable for error-resilient applications like preconditioning even for ill-conditioned matrices. We discuss the execution time and scaling of the algorithm on a theoretical level and present a distributed implementation of the algorithm using MPI and OpenMP. We demonstrate the scalability of this implementation by running it on a high-performance compute cluster comprised of 1024 CPU cores, showing a speedup of 665x compared to single-threaded execution.

Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots

M. Lass, T. Kühne, C. Plessl, Embedded Systems Letters (2018), 10(2), pp. 33-36

Approximate computing has shown to provide new ways to improve performance and power consumption of error-resilient applications. While many of these applications can be found in image processing, data classification or machine learning, we demonstrate its suitability to a problem from scientific computing. Utilizing the self-correcting behavior of iterative algorithms, we show that approximate computing can be applied to the calculation of inverse matrix p-th roots which are required in many applications in scientific computing. Results show great opportunities to reduce the computational effort and bandwidth required for the execution of the discussed algorithm, especially when targeting special accelerator hardware.


Flexible FPGA design for FDTD using OpenCL

T. Kenter, J. Förstner, C. Plessl, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017

Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures.


Microdisk Cavity FDTD Simulation on FPGA using OpenCL

T. Kenter, C. Plessl, in: Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC), 2016

Open list in Research Information System


Prof. Dr. Christian Plessl

Paderborn Center for Parallel Computing (PC2)

Christian Plessl
+49 5251 60-5399
+49 5251 60-1714

Dr. Tobias Kenter

Paderborn Center for Parallel Computing (PC2)

Scientific Advisor FPGA Acceleration

+49 5251 60-4340
+49 5251 60-1714

Dr. Michael Laß

Paderborn Center for Parallel Computing (PC2)

Scientific Advisor Numerical Libraries for CSE

Michael Laß
+49 5251 60-1722
+49 5251 60-1714

The University for the Information Society