Achtung:

Sie haben Javascript deaktiviert!
Sie haben versucht eine Funktion zu nutzen, die nur mit Javascript möglich ist. Um sämtliche Funktionalitäten unserer Internetseite zu nutzen, aktivieren Sie bitte Javascript in Ihrem Browser.

Data Center Building O Show image information

Data Center Building O

All Publications


Open list in Research Information System

2018

A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems

A. Keller, in: Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), Springer, 2018, pp. 132-151

DOI
Abstract

This paper describes a data structure and a heuristic to plan and map arbitrary resources in complex combinations while applying time dependent constraints. The approach is used in the planning based workload manager OpenCCS at the Paderborn Center for Parallel Computing (PC\(^2\)) to operate heterogeneous clusters with up to 10000 cores. We also show performance results derived from four years of operation.


A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices

D. Richters, M. Lass, A. Walther, C. Plessl, T. Kühne, Communications in Computational Physics (2018)

arXiv
Abstract

We address the general mathematical problem of computing the inverse p-th root of a given matrix in an efficient way. A new method to construct iteration functions that allow calculating arbitrary p-th roots and their inverses of symmetric positive definite matrices is presented. We show that the order of convergence is at least quadratic and that adaptively adjusting a parameter q always leads to an even faster convergence. In this way, a better performance than with previously known iteration schemes is achieved. The efficiency of the iterative functions is demonstrated for various matrices with different densities, condition numbers and spectral radii.


A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices

M. Lass, S. Mohr, H. Wiebeler, T. Kühne, C. Plessl, in: Proc. Platform for Advanced Scientific Computing Conference (PASC), ACM, 2018


Automated Code Acceleration Targeting Heterogeneous OpenCL Devices

H. Riebler, G.F. Vaz, T. Kenter, C. Plessl, in: Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming - PPoPP '18, ACM Press, 2018

DOI

OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes

T. Kenter, G. Mahale, S. Alhaddad, Y. Grynko, C. Schmitt, A. Afzal, F. Hannig, J. Förstner, C. Plessl, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018


2017

Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs

H. Riebler, M. Lass, R. Mittendorf, T. Löcke, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems (TRETS) (2017), pp. 24:1-24:23

DOI
Abstract

Branch and bound (B&B) algorithms structure the search space as a tree and eliminate infeasible solutions early by pruning subtrees that cannot lead to a valid or optimal solution. Custom hardware designs significantly accelerate the execution of these algorithms. In this article, we demonstrate a high-performance B&B implementation on FPGAs. First, we identify general elements of B&B algorithms and describe their implementation as a finite state machine. Then, we introduce workers that autonomously cooperate using work stealing to allow parallel execution and full utilization of the target FPGA. Finally, we explore advantages of instance-specific designs that target a specific problem instance to improve performance. We evaluate our concepts by applying them to a branch and bound problem, the reconstruction of corrupted AES keys obtained from cold-boot attacks. The evaluation shows that our work stealing approach is scalable with the available resources and provides speedups proportional to the number of workers. Instance-specific designs allow us to achieve an overall speedup of 47 × compared to the fastest implementation of AES key reconstruction so far. Finally, we demonstrate how instance-specific designs can be generated just-in-time such that the provided speedups outweigh the additional time required for design synthesis.


Flexible FPGA design for FDTD using OpenCL

T. Kenter, J. Förstner, C. Plessl, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017

DOI

High-Throughput and Low-Latency Network Communication with NetIO

J. Schumacher, C. Plessl, W. Vandelli, Journal of Physics: Conference Series (2017)

DOI

Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots

M. Lass, T. Kühne, C. Plessl, Embedded Systems Letters (2017)

arXiv
Abstract

Approximate computing has shown to provide new ways to improve performance and power consumption of error-resilient applications. While many of these applications can be found in image processing, data classification or machine learning, we demonstrate its suitability to a problem from scientific computing. Utilizing the self-correcting behavior of iterative algorithms, we show that approximate computing can be applied to the calculation of inverse matrix p-th roots which are required in many applications in scientific computing. Results show great opportunities to reduce the computational effort and bandwidth required for the execution of the discussed algorithm, especially when targeting special accelerator hardware.


2016

Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension

M. Lass, D. Leibenger, C. Sorge, in: Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016

DOI
Abstract

Version Control Systems (VCS) are a valuable tool for software development and document management. Both client/server and distributed (Peer-to-Peer) models exist, with the latter (e.g., Git and Mercurial) becoming increasingly popular. Their distributed nature introduces complications, especially concerning security: it is hard to control the dissemination of contents stored in distributed VCS as they rely on replication of complete repositories to any involved user. We overcome this issue by designing and implementing a concept for cryptography-enforced access control which is transparent to the user. Use of field-tested schemes (end-to-end encryption, digital signatures) allows for strong security, while adoption of convergent encryption and content-defined chunking retains storage efficiency. The concept is seamlessly integrated into Mercurial---respecting its distributed storage concept---to ensure practical usability and compatibility to existing deployments.


Microdisk Cavity FDTD Simulation on FPGA using OpenCL

T. Kenter, C. Plessl, in: Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC), 2016


Modeling and simulation of metallic, particle-damped spheres for lightweight materials

T. Steinle, 2016

Abstract

Lightweight materials play an ever growing role in today's world. Saving on the mass of a machine will usually translate into a lower energy consumption. However, lightweight applications are prone to develop performance problems due to vibration induced by the operation of the machine. The Fraunhofer Institute for Manufacturing Technology and Advanced Materials in Dresden conducts research into the damping properties of composite materials. They are experimenting with hollow, particle filled spheres embedded in the lightweight material. Such a system is the technical motivation of this thesis. Ultimately, a numerical experiment to derive the coefficient of restitution is required. The simulation developed in this thesis is based on a discrete element method to track the individual particle and sphere trajectories. Based on a potential based approach for the particle interactions deployed in molecular dynamics, the behavior of the particles can be controlled effectively. The simulated volume is using reflecting boundaries and encloses the hollow sphere. In this work, a highly flexible memory structure was used with a linked cell approach to cope with the highly flexible mass of particles. This allows for a linear complexity of the method in regard to the particle number by reducing the computational overhead of the interaction computation. Multiple numerical experiments show the great effect the particles have on the damping behavior of the system.


Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control

M. Dellnitz, J. Eckstein, K. Flaßkamp, P. Friedel, C. Horenkamp, U. Köhler, S. Ober-Blöbaum, S. Peitz, S. Tiemeyer, in: Progress in Industrial Mathematics at ECMI, Springer International Publishing, 2016, pp. 633-641

DOI

Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)

T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable Computing (WRC), 2016


Performance-centric scheduling with task migration for a heterogeneous compute node in the data center

A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912-917

Abstract

The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative.


Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code

G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, Computers and Electrical Engineering (2016), pp. 91-111

DOI
Abstract

A broad spectrum of applications can be accelerated by offloading computation intensive parts to reconfigurable hardware. However, to achieve speedups, the number of loop it- erations (trip count) needs to be sufficiently large to amortize offloading overheads. Trip counts are frequently not known at compile time, but only at runtime just before entering a loop. Therefore, we propose to generate code for both the CPU and the coprocessor, and defer the offloading decision to the application runtime. We demonstrate how a toolflow, based on the LLVM compiler framework, can automatically embed dynamic offloading de- cisions into the application code. We perform in-depth static and dynamic analysis of pop- ular benchmarks, which confirm the general potential of such an approach. We also pro- pose to optimize the offloading process by decoupling the runtime decision from the loop execution (decision slack). The feasibility of our approach is demonstrated by a toolflow that automatically identifies suitable data-parallel loops and generates code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow with representative loops executed for different input data sizes.



ReconOS

A. Agne, M. Platzner, C. Plessl, M. Happe, E. Lübbers, in: FPGAs for Software Programmers, Springer International Publishing, 2016, pp. 227-244

DOI

Second harmonic generation spectroscopy on hybrid plasmonic/dielectric nanoantennas

H. Linnenbank, Y. Grynko, J. Förstner, S. Linden, Light: Science & Applications (2016)

DOI

Self-aware Compute Nodes

A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, in: Self-aware Computing Systems, Springer International Publishing, 2016, pp. 145-165

DOI
Abstract

Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level.


Using Approximate Computing in Scientific Codes

M. Lass, T. Kühne, C. Plessl, in: Workshop on Approximate Computing (AC), 2016


Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems

H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, C. Bolchini, in: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016


Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems

H. Riebler, G.F. Vaz, C. Plessl, E.M.G.. Trainiti, G.C. Durelli, E. Del Sozzo, M.D.. Santambrogio, C. Bolchini, in: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1-5

DOI
Abstract

Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads.


2015

Aktuelles Schlagwort: Approximate Computing

C. Plessl, M. Platzner, P.J. Schreier, Informatik Spektrum (2015), pp. 396-399

DOI

Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores

M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT), 2015

Abstract

This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement.


Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study

T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable Computing (IJRC) (2015)

DOI
Abstract

FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x.


FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades

J. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. Schreuder, J. Schumacher, W. Vandelli, J. Vermeulen, J. Zhang, Journal of Physics: Conference Series (2015)

DOI
Abstract

The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented and hardware and software aspects will be discussed.


Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm

J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015

DOI

Localization and Analysis of Code Paths Suitable for Acceleration using Approximate Computing

M. Lass. Localization and Analysis of Code Paths Suitable for Acceleration using Approximate Computing. 2015.

Abstract

Demands for computational power and energy efficiency of computing devices are steadily increasing. At the same time, following classic methods to increase speed and reduce energy consumption of these devices becomes increasingly difficult, bringing alternative methods into focus. One of these methods is approximate computing which utilizes the fact that small errors in computations are acceptable in many applications in order to allow acceleration of these computations or to increase energy efficiency. This thesis develops elements of a workflow that can be followed to apply approximate computing to existing applications. It proposes a novel heuristic approach to the localization of code paths that are suitable to approximate computing based on findings in recent research. Additionally, an approach to identification of approximable instructions within these code paths is proposed and used to implement simulation of approximation. The parts of the workflow are implemented with the goal to lay the foundation for a partly automated toolflow. Evaluation of the developed techniques shows that the proposed methods can help providing a convenient workflow, facilitating the first steps into the application of approximate computing.


Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction

S. Peitz, M. Dellnitz, PAMM (2015), pp. 613-614

DOI
Abstract

In this article an efficient numerical method to solve multiobjective optimization problems for fluid flow governed by the Navier Stokes equations is presented. In order to decrease the computational effort, a reduced order model is introduced using Proper Orthogonal Decomposition and a corresponding Galerkin Projection. A global, derivative free multiobjective optimization algorithm is applied to compute the Pareto set (i.e. the set of optimal compromises) for the concurrent objectives minimization of flow field fluctuations and control cost. The method is illustrated for a 2D flow around a cylinder at Re = 100.


Self-Aware and Self-Expressive Systems – Guest Editor's Introduction

J. Torresen, C. Plessl, X. Yao, IEEE Computer (2015), pp. 18-20

DOI

Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung

S. Hegler, C. Statz, M. Mütze, H. Mooshofer, M. Goldammer, K. Fendt, S. Schwarzer, K. Feldhoff, M. Flehmig, U. Markwardt, W. E. Nagel, M. Schütte, A. Walther, M. Meinel, A. Basermann, D. Plettemeier, tm - Technisches Messen (2015), pp. 440-450

DOI
Abstract

Große zylindrische Stahlprüflinge werden mittels der Methode der finiten Differenzen im Zeitbereich (engl. finite differences in time domain, FDTD) simulativ untersucht. Dabei werden Pitch-Catch-Messanordnungen verwendet. Es werden zwei Bildgebungsansätze vorgestellt: ersterer basiert auf dem Imaging Principle nach Claerbout, letzterer basiert auf gradientenbasierter Optimierung eines Zielfunktionals.


Transparent offloading of computational hotspots from binary code to Xeon Phi

M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078-1083

DOI
Abstract

In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator.


2014

Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers

H. Giefers, C. Plessl, J. Förstner, ACM SIGARCH Computer Architecture News (2014), pp. 65-70

DOI

Deferring Accelerator Offloading Decisions to Application Runtime

G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1-8

DOI
Abstract

Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes.


Kernel-Centric Acceleration of High Accuracy Stereo-Matching

T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1-8

DOI
Abstract

Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design.


Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres

T. Steinle, J. Vrabec, A. Walther, in: Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), Springer International Publishing, 2014, pp. 233-243

DOI
Abstract

In light of an increasing awareness of environmental challenges, extensive research is underway to develop new light-weight materials. A problem arising with these materials is their increased response to vibration. This can be solved using a new composite material that contains embedded hollow spheres that are partially filled with particles. Progress on the adaptation of molecular dynamics towards a particle-based numerical simulation of this material is reported. This includes the treatment of specific boundary conditions and the adaption of the force computation. First results are presented that showcase the damping properties of such particle-filled spheres in a bouncing experiment.


On Semeai Detection in Monte-Carlo Go

T. Graf, L. Schaefers, M. Platzner, in: Proc. Conf. on Computers and Games (CG), Springer, 2014, pp. 14-25

DOI

Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer

T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, 2014, pp. 144-155

DOI
Abstract

In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties.


ReconOS - An Operating System Approach for Reconfigurable Computing

A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl, IEEE Micro (2014), pp. 60-71

DOI
Abstract

The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications


Reconstructing AES Key Schedules from Decayed Memory with FPGAs

H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222-229

DOI
Abstract

In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates.


Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach

G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142-149

DOI

SAVE: Towards efficient resource management in heterogeneous system architectures

G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014

DOI

Self-awareness as a Model for Designing and Operating Heterogeneous Multicores

A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (TRETS) (2014)

DOI
Abstract

Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems.


Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators

A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and Microsystems (2014), pp. 911-919

DOI
Abstract

Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.


Verschiebungen an der Grenze zwischen Hardware und Software

M. Platzner, C. Plessl, in: Logiken strukturbildender Prozesse: Automatismen, Wilhelm Fink, 2014, pp. 123-144

Abstract

Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung von neuen Forschungsrichtungen gef{\"u}hrt. In diesem Beitrag besch{\"a}ftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\"a}ndige Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\"u}hrt hat. Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software w{\"a}hrend der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen k{\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom w{\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers w{\"a}hrend der Laufzeit ver{\"a}ndert werden kann. Diese Technologie f{\"u}hrt zu einer durchl{\"a}ssigen Grenze zwischen Hardware und Software bzw. l{\"o}st sie die herk{\"o}mmliche Vorstellung einer festen Hardware und einer flexiblen Software damit auf.


2013

Advanced Data Deduplication Techniques and Their Application

D. Meister, Johannes Gutenberg-Universität Mainz, 2013



Distributing Storage in Cloud Environments

P. Berenbrink, A. Brinkmann, T. Friedetzky, D. Meister, L. Nagel, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE, 2013

DOI

File Recipe Compression in Data Deduplication Systems

D. Meister, A. Brinkmann, T. Süß, in: Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX Association, 2013, pp. 175-182


FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm

S. Kasap, S. Redif, in: Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013

DOI

FPGA-accelerated Key Search for Cold-Boot Attacks against AES

H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386-389

DOI
Abstract

Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES.


Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs

H. Riebler. Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. 2013.


Light scattering by randomly irregular dielectric particles larger than the wavelength

Y. Grynko, Y. Shkuratov, J. Förstner, Optical Letters (2013), pp. 5153-5156

DOI

MCD: Overcoming the Data Download Bottleneck in Data Centers

J. Kaiser, D. Meister, V. Gottfried, A. Brinkmann, in: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE Computer Society, 2013, pp. 88-97

DOI

Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices

S. Kasap, S. Redif, IEEE Trans. on Very Large Scale Integration (VLSI) Systems (2013), pp. 522-536

DOI

On-The-Fly Computing: A Novel Paradigm for Individualized IT Services

M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in: Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS), IEEE, 2013

DOI
Abstract

In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas.


Parallel Macro Pipelining on the Intel SCC Many-Core Computer

T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, 2013, pp. 64-73

DOI

2012

A Data Driven Science Gateway for Computational Workflows

R. Grunzke, G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, S. Gesing, S. Herres-Pawlis, O. Kohlbacher, J. Krüger, M. Kruse, R. Müller-Pfefferkorn, P. Schäfer, B. Schuller, T. Steinke, A. Zink, in: Proc. UNICORE Summit, 2012


A Science Gateway Getting Ready for Serving the International Molecular Simulation Community

S. Gesing, S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, R. Grunzke, P. Kacsuk, O. Kohlbacher, M. Kozlovszky, J. Krüger, R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, in: Proceedings of Science, 2012


A Single Sign-On Infrastructure for Science Gateways on a Use Case for Structural Bioinformatics

S. Gesing, R. Grunzke, J. Krüger, G. Birkenheuer, M. Wewior, P. Schäfer, B. Schuller, J. Schuster, S. Herres-Pawlis, S. Breuers, Balaskó, M. Kozlovszky, A. Szikszay Fabri, L. Packschies, P. Kacsuk, D. Blunk, T. Steinke, A. Brinkmann, G. Fels, R. Müller-Pfefferkorn, R. Jäkel, O. Kohlbacher, Journal of Grid Computing (2012), pp. 769-790

DOI

A Study on Data Deduplication in HPC Storage Systems

D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, T. Cortes, in: Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, 2012, pp. 7:1-7:11

DOI

Comparison of Bayesian Move Prediction Systems for Computer Go

M. Wistuba, L. Schaefers, M. Platzner, in: Proc. IEEE Conf. on Computational Intelligence and Games (CIG), IEEE, 2012, pp. 91-99

DOI

Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?

B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189-196

DOI

Cost-aware and SLO Fulfilling Software as a Service

O. Niehörster, J. Simon, A. Brinkmann, A. Keller, J. Krüger, Journal of Grid Computing (2012), pp. 553-577

DOI
Abstract

Virtualization technology makes data centers more dynamic and easier to administrate. Today, cloud providers offer customers access to complex applications running on virtualized hardware. Nevertheless, big virtualized data centers become stochastic environments and the simplification on the user side leads to many challenges for the provider. He has to find cost-efficient configurations and has to deal with dynamic environments to ensure service level objectives (SLOs). We introduce a software solution that reduces the degree of human intervention to manage clouds. It is designed as a multi-agent system (MAS) and placed on top of the Infrastructure as a Service (IaaS) layer. Worker agents allocate resources, configure applications, check the feasibility of requests, and generate cost estimates. They are equipped with application specific knowledge allowing it to estimate the type and number of necessary resources. During runtime, a worker agent monitors the job and adapts its resources to ensure the specified quality of service—even in noisy clouds where the job instances are influenced by other jobs. They interact with a scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low costs. The whole architecture is self-optimizing and able to use public or private clouds. Building a private cloud needs to face the challenge to find a mapping of virtual machines (VMs) to hosts. We present a rule-based mapping algorithm for VMs. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. An energy-aware scheduler and the availability of cheap resources provided by a spot market are analyzed. We evaluated our approach by building up an SaaS stack, which assigns resources in consideration of an energy function and that ensures SLOs of two different applications, a brokerage system and a high-performance computing software. Experiments were done on a real cloud system and by simulations.


Design of an exact data deduplication cluster

J. Kaiser, D. Meister, A. Brinkmann, S. Effert, in: Proc. Symp. on Mass Storage Systems and Technologies (MSST), IEEE, 2012, pp. 1-12

DOI

Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators

M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1-8

DOI
Abstract

Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices.


ESB: Ext2 Split Block Device

J. Kaiser, D. Meister, T. Hartung, A. Brinkmann, in: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181-188

DOI

Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs

C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559-562

DOI
Abstract

While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA.


FPGA implementation of a second-order convolutive blind signal separation algorithm

S. Kasap, S. Redif, in: Int. Architecture and Engineering Symp. (ARCHENG), 2012


FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm

S. Kasap, S. Redif, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135-140

DOI

Generic User Management for Science Gateways via Virtual Organizations

T. Schlemmer, R. Grunzke, S. Gesing, J. Krüger, G. Birkenheuer, R. Müller-Pfefferkorn, O. Kohlbacher, in: Proc. EGI Technical Forum, 2012


Hardware/Software Platform for Self-aware Compute Nodes

M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8-9

Abstract

Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method.


IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators

T. Schumacher, C. Plessl, M. Platzner, Microprocessors and Microsystems (2012), pp. 110-126

DOI

On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors

M. Grad, C. Plessl, Int. Journal of Reconfigurable Computing (IJRC) (2012)

DOI

One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services

G. Congiu, M. Grawinkel, S. Narasimhamurthy, A. Brinkmann, in: Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), IEEE, 2012, pp. 16-24

DOI

Parallel algorithm for computation of second-order sequential best rotations

S. Redif, S. Kasap, Int. Journal of Electronics (2012), pp. 1646-1651

DOI

Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer

S. Kasap, K. Benkrid, Journal of Computers (2012), pp. 1312-1328


Pragma based parallelization - Trading hardware efficiency for ease of use?

T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1-8

DOI
Abstract

One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.


Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux

T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS), 2012


Programming models for reconfigurable heterogeneous multi-cores

C. Plessl, M. Platzner, A. Agne, M. Happe, E. Lübbers, Awareness Magazine (2012)

DOI

STIR: Software for Tomographic Image Reconstruction Release 2

K. Thielemans, C. Tsoumpas, S. Mustafovic, T. Beisel, P. Aguiar, N. Dikaios, M. W Jacobson, Physics in Medicine and Biology (2012), pp. 867-883

DOI

The MoSGrid Community From National to International Scale

S. Gesing, S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, R. Grunzke, P. Kacsuk, O. Kohlbacher, M. Kozlovszky, J. Krüger, R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, in: Proc. EGI Community Forum, 2012


Towards Dynamic Scripted pNFS Layouts

M. Grawinkel, T. Süß, G. Best, I. Popov, A. Brinkmann, in: Proc. Parallel Data Storage Workshop (PDSW), IEEE, 2012, pp. 13-17

DOI

Turning control flow graphs into function calls: Code generation for heterogeneous architectures

P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559-565

DOI
Abstract

Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided.


Workflow-enhanced conformational analysis of guanidine zinc complexes via a science gateway

S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, S. Gesing, R. Grunzke, R. Jäkel, O. Kohlbacher, J. Krüger, I. Dos Santos Vieira, Studies in Health Technology and Informatics (2012), pp. 142-151

DOI

2011

A Science Gateway for Molecular Simulations

S. Gesing, P. Kacsuk, M. Kozlovszky, G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, G. Fels, R. Grunzke, S. Herres-Pawlis, J. Krüger, L. Packschies, R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, A. Szikszay Fabri, K. Warzecha, M. Wewior, O. Kohlbacher, in: Proc. EGI User Forum, 2011, pp. 94-95


An Energy-Aware SaaS Stack

O. Niehörster, A. Keller, A. Brinkmann, in: Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011

DOI
Abstract

We present a multi-agent system on top of the IaaS layer consisting of a scheduler agent and multiple worker agents. Each job is controlled by an autonomous worker agent, which is equipped with application specific knowledge (e.g., performance functions) allowing it to estimate the type and number of necessary resources. During runtime, the worker agent monitors the job and adapts its resources to ensure the specified quality of service - even in noisy clouds where the job instances are influenced by other jobs. All worker agents interact with the scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low energy costs. The whole architecture is self-optimizing and able to use public or private clouds.


Autonomic Resource Management Handling Delayed Configuration Effects

O. Niehörster, A. Brinkmann, in: Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom), IEEE Computer Society, 2011, pp. 138-145

DOI

Autonomic Resource Management with Support Vector Machines

O. Niehörster, J. Simon, A. Brinkmann, A. Krieger, in: Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID), IEEE Computer Society, 2011, pp. 157-164

DOI

Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler

T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223-226

DOI

Estimation and Partitioning for CPU-Accelerator Architectures

T. Kenter, C. Plessl, M. Platzner, M. Kauschke, in: Intel European Research and Innovation Conference, 2011


Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability

M. Grawinkel, T. Schäfer, A. Brinkmann, J. Hagemeyer, M. Porrmann, in: Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), IEEE Computer Society, 2011, pp. 297-306

DOI

FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study

T. Schumacher, T. Süß, C. Plessl, M. Platzner, Int. Journal of Recon- figurable Computing (IJRC) (2011)

DOI

Granular Security for a Science Gateway in Structural Bioinformatics

S. Gesing, R. Grunzke, Balaskó, G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, G. Fels, S. Herres-Pawlis, P. Kacsuk, M. Kozlovszky, J. Krüger, L. Packschies, P. Schäfer, B. Schuller, J. Schuster, T. Steinke, A. Szikszay Fabri, M. Wewior, R. Müller-Pfefferkorn, O. Kohlbacher, in: Proc. Int. Workshop on Scientific Gateways (IWSG), Consorzio COMETA, 2011


Hardware Virtualization on Dynamically Reconfigurable Embedded Processors

C. Plessl, M. Platzner, in: Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, IGI Global, 2011

DOI

Infrastructure Federation Through Virtualized Delegation of Resources and Services

G. Birkenheuer, A. Brinkmann, M. Högqvist, A. Papaspyrou, B. Schott, D. Sommerfeld, W. Ziegler, Journal of Grid Computing (2011), pp. 355-377

DOI

Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture

M. Grad, C. Plessl, in: Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278-285

DOI

Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System

M. Grawinkel, M. Pargmann, H. Dömer, A. Brinkmann, in: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2011, pp. 380-387

DOI

Measuring and Predicting Temperature Distributions on FPGAs at Run-Time

M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55-60

DOI
Abstract

In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time.


MoSGrid: Progress of Workflow driven Chemical Simulations

G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, G. Fels, S. Gesing, R. Grunzke, S. Herres-Pawlis, O. Kohlbacher, J. Krüger, U. Lang, L. Packschies, R. Müller-Pfefferkorn, P. Schäfer, J. Schuster, T. Steinke, K. Warzecha, M. Wewior, in: Proc. of Grid Workflow Workshop (GWW), 2011


Parallel Monte-Carlo Tree Search for HPC Systems

T. Graf, U. Lorenz, M. Platzner, L. Schaefers, in: Proc. European Conf. on Parallel Processing (Euro-Par), Springer, 2011

DOI

Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures

T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, 2011, pp. 177-180

DOI

Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems

A. Miranda, S. Effert, Y. Kang, E. Miller, A. Brinkmann, T. Cortes, in: Proc. Int. Conf. on High Performance Computing (HIPC), IEEE Computer Society, 2011, pp. 1-10

DOI

Request Load Balancing for Highly Skewed Traffic in P2P Networks

A. Brinkmann, Y. Gao, M. Korzeniowski, D. Meister, in: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE, 2011, pp. 53-62

DOI

Rule Based Mapping of Virtual Machines in Clouds

C. Kleineweber, A. Keller, O. Niehörster, A. Brinkmann, in: Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011

DOI
Abstract

Infrastructure as a Service providers use virtualization to abstract their hardware and to create a dynamic data center. Virtualization enables the consolidation of virtual machines as well as the migration of them to other hosts during runtime. Each provider has its own strategy to efficiently operate a data center. We present a rule based mapping algorithm for VMs, which is able to automatically adapt the mapping between VMs and physical hosts. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. We extended the open source IaaS solution Eucalyptus and we evaluated it with typical policies: maximizing the compute performance and VM locality to achieve a high performance and minimizing energy consumption. The evaluation was done on state-of-the-art servers in our own data center and by simulations using a workload of the Parallel Workload Archive. The results show that our algorithm performs well in dynamic data centers environments.


Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend

B. Meyer, C. Plessl, J. Förstner, in: Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60-63

DOI

Virtualized HPC: a contradiction in terms?

G. Birkenheuer, A. Brinkmann, J. Kaiser, A. Keller, M. Keller, C. Kleineweber, C. Konersmann, O. Niehörster, T. Schäfer, J. Simon, M. Wilhelm, Software: Practice and Experience (2011)

DOI
Abstract

System virtualization has become the enabling technology to manage the increasing number of different applications inside data centers. The abstraction from the underlying hardware and the provision of multiple virtual machines (VM) on a single physical server have led to a consolidation and more efficient usage of physical servers. The abstraction from the hardware also eases the provision of applications on different data centers, as applied in several cloud computing environments. In this case, the application need not adapt to the environment of the cloud computing provider, but can travel around with its own VM image, including its own operating system and libraries. System virtualization and cloud computing could also be very attractive in the context of high‐performance computing (HPC). Today, HPC centers have to cope with both, the management of the infrastructure and also the applications. Virtualization technology would enable these centers to focus on the infrastructure, while the users, collaborating inside their virtual organizations (VOs), would be able to provide the software. Nevertheless, there seems to be a contradiction between HPC and cloud computing, as there are very few successful approaches to virtualize HPC centers. This work discusses the underlying reasons, including the management and performance, and presents solutions to overcome the contradiction, including a set of new libraries. The viability of the presented approach is shown based on evaluating a selected parallel, scientific application in a virtualized HPC environment.


2010

An Open Source Circuit Library with Benchmarking Facilities

M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144-150


Balls into Bins with Related Random Choices

P. Berenbrink, A. Brinkmann, T. Friedetzky, L. Nagel, in: Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA), ACM, 2010, pp. 100-105

DOI

Balls into Non-uniform Bins

P. Berenbrink, A. Brinkmann, T. Friedetzky, L. Nagel, in: Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS), IEEE, 2010, pp. 1-10

DOI

Configurable Processor Architectures: History and Trends

D. Andrews, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 165


dedupv1: Improving Deduplication Throughput using Solid State Drives (SSD)

D. Meister, A. Brinkmann, in: Proc. Symp. on Mass Storage Systems and Technologies (MSST), IEEE Computer Society, 2010, pp. 1-6

DOI

Enforcing SLAs in Scientific Clouds

O. Niehörster, A. Brinkmann, G. Fels, J. Krüger, J. Simon, in: Proc. Int. Conf. on Cluster Computing (CLUSTER), IEEE, 2010, pp. 178-187

DOI

Grid-Workflows in Molecular Science

G. Birkenheuer, S. Breuers, A. Brinkmann, D. Blunk, G. Fels, S. Gesing, S. Herres-Pawlis, O. Kohlbacher, J. Krüger, L. Packschies, in: Proc. of Grid Workflow Workshop (GWW), Gesellschaft für Informatik (GI), 2010, pp. 177-184


hashFS: Applying Hashing to Optimized File Systems for Small File Reads

P.H. Lensing, D. Meister, A. Brinkmann, in: Proc. Int. Worksh. on Storage Network Architecture and Parallel I/Os (SNAPI), IEEE, 2010, pp. 33-42

DOI

Non-intrusive Virtualization Management Using libvirt

M. Bolte, M. Sievers, G. Birkenheuer, O. Niehörster, A. Brinkmann, in: Proc. Design, Automation and Test in Europe Conf. (DATE), EDA Consortium, 2010


Open Source Middleware for Networked Embedded Systems towards Future Internet of Things

N. R. Prasad, M. Eisenhauer, M. Ahlsén, A. Badii, A. Brinkmann, K. Marius Hansen, P. Rosengren, in: Vision and Challenges for Realising the Internet of Things, European Commission, 2010, pp. 153-163


Performance Estimation for the Exploration of CPU-Accelerator Architectures

T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), 2010


Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)

T.P. Plaks, D. Andrews, R. DeMara, H. Lam, J. Lee, C. Plessl, G. Stitt, CSREA Press, 2010


Pruning the Design Space for Just-In-Time Processor Customization

M. Grad, C. Plessl, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2010, pp. 67-72

DOI

Reconfigurable Nodes for Future Networks

A. Keller, B. Plattner, E. Lübbers, M. Platzner, C. Plessl, in: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372-376

DOI

Reliability Analysis of Declustered-Parity RAID 6 with Disk Scrubbing and Considering Irrecoverable Read Errors

Y. Gao, D. Meister, A. Brinkmann, in: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE, 2010, pp. 126-134

DOI

Risikomanagement für verteilte Umgebungen

A. Brinkmann, D. Battré, G. Birkenheuer, O. Kao, K. Voß, ForschungsForum Paderborn (2010)


Risk Aware Overbooking for Commercial Grids

G. Birkenheuer, A. Brinkmann, H. Karl, in: Job Scheduling Strategies for Parallel Processing - 15th International Workshop, JSSPP 2010, Atlanta, GA, USA, April 23, 2010, Revised Selected Papers, 2010, pp. 51-76

DOI

Rupeas: Ruby Powered Event Analysis DSL

M. Woehrle, C. Plessl, L. Thiele, in: Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, 2010, pp. 245-248

DOI

SkewCCC+: A Heterogeneous Distributed Hash Table

M. Bienkowski, A. Brinkmann, M. Klonowski, M. Korzeniowski, in: Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis), Springer, 2010

DOI

The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations

M. Wewior, L. Packschies, D. Blunk, D. Wickeroth, K. Warzecha, S. Herres-Pawlis, S. Gesing, S. Breuers, J. Krüger, G. Birkenheuer, U. Lang, in: Proc. Int. Workshop on Scientific Gateways (IWSG), Consorzio COMETA, 2010, pp. 39-43


Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware

E. Lübbers, M. Platzner, C. Plessl, A. Keller, B. Plattner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225-231


Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators

T. Beisel, M. Niekamp, C. Plessl, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp. 65-72

DOI

Workflow Interoperability in a Grid Portal for Molecular Simulations

S. Gesing, I. Marton, G. Birkenheuer, B. Schuller, R. Grunzke, J. Krüger, S. Breuers, D. Blunk, G. Fels, L. Packschies, A. Brinkmann, O. Kohlbacher, M. Kozlovszky, in: Proc. Int. Workshop on Scientific Gateways (IWSG), Consorzio COMETA, 2010, pp. 44-48


2009

A Microdriver Architecture for Error Correcting Codes inside the Linux Kernel

A. Brinkmann, D. Eschweiler, Journal of Supercomputing (2009), pp. 35:1-35:10

DOI

An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure

T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338-344


An Orchestration as a Service Infrastructure using Grid Technologies and WS-BPEL

A. Höing, G. Scherp, S. Gudenkauf, D. Meister, A. Brinkmann, in: Proc. Int. Conf. on Service Oriented Computing (ICSOC), Springer, 2009, pp. 301-315

DOI

Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000

T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2009, pp. 119-124

DOI

Connecting Communities on the Meta-Scheduling Level: The DGSI Approach!

G. Birkenheuer, A. Carlson, A. Fölling, M. Högqvist, A. Hoheisel, A. Papaspyrou, K. Rieger, B. Schott, W. Ziegler, in: Proc. Cracow Grid Workshop (CGW), 2009, pp. 96-103


EvoCaches: Application-specific Adaptation of Cache Mapping

P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, 2009, pp. 11-18

Abstract

In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable.


IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing

T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275-278

DOI
Abstract

Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator.


Multi-Level Comparison of Data Deduplication in a Backup Scenario

D. Meister, A. Brinkmann, in: Proc. of the Israeli Experimental Systems Conference (SYSTOR), ACM, 2009, pp. 8:1-8:12

DOI

PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes

J. Beutel, S. Gruber, A. Hasler, R. Lim, A. Meier, C. Plessl, I. Talzi, L. Thiele, C. Tschudin, M. Woehrle, M. Yuecel, in: Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), IEEE Computer Society, 2009, pp. 265-276


Providing Scientific Software as a Service in Consideration of Service Level Agreements

O. Niehörster, G. Birkenheuer, A. Brinkmann, D. Blunk, B. Elsässer, S. Herres-Pawlis, J. Krüger, J. Niehörster, L. Packschies, G. Fels, in: Proc. Cracow Grid Workshop (CGW), 2009, pp. 55-63


Rupeas: Ruby Powered Event Analysis DSL

M. Woehrle, C. Plessl, L. Thiele, 2009

Abstract

Wireless Sensor Networks (WSNs) are unique embedded computation systems for distributed sensing of a dispersed phenomenon. While being a strongly concurrent distributed system, its embedded aspects with severe resource limitations and the wireless communication requires a fusion of technologies and methodologies from very different fields. As WSNs are deployed in remote locations for long-term unattended operation, assurance of correct functioning of the system is of prime concern. Thus, the design and development of WSNs requires specialized tools to allow for testing and debugging the system. To this end, we present a framework for analyzing and checking WSNs based on collected events during system operation. It allows for abstracting from the event trace by means of behavioral queries and uses assertions for checking the accordance of an execution to its specification. The framework is independent from WSN test platforms, applications and logging semantics and thus generally applicable for analyzing event logs of WSN test executions.


The Gain of Overbooking

G. Birkenheuer, A. Brinkmann, H. Karl, in: Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers, 2009, pp. 80-100

DOI

Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX

M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2009, pp. 319-322

Abstract

In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit.


2008

A Hardware Accelerator for k-th Nearest Neighbor Thinning

T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245-251


A method for OSEM PET reconstruction on parallel architectures using STIR

T. Beisel, S. Lietsch, K. Thielemans, in: IEEE Nuclear Science Symposium Conference Record (NSS), IEEE, 2008, pp. 4161-4168

DOI

Applying Risk Management to Support SLA Provisioning

D. Battre, G. Birkenheuer, M. Hovestadt, O. Kao, K. Voss, in: Proc. Cracow Grid Workshop (CGW), 2008


Computational Steering Of Interactive Material Flow Simulations

S. Lietsch, H. Zabel, C. Laroque, in: Proc. ASME Computers and Information in Engineering Conference (CIE), ASME, 2008, pp. 1493-1502

DOI

Computational Steering verteilter, interaktiver Materialflusssimulationen

C. Laroque, S. Lietsch, H. Zabel, in: Augmented & Virtual Reality in der Produktentstehung, Heinz Nixdorf Institut, 2008, pp. 221-239


CUDA-based, parallel JPEG Compression for Remote Rendering

S. Lietsch, P. Hermann Lensing, in: Proc. Int. Symp. on Image/Video Communications over fixed and mobile networks (ISVC), IEEE, 2008


Data Replication in P2P Environments

A. Brinkmann, S. Effert, in: Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA), ACM, 2008, pp. 191-193

DOI

Degree 3 Suffices: A Large-Scale Overlay for P2P Networks

M. Bienkowski, A. Brinkmann, M. Korzeniowski, in: Proc. Int. Conf. on Principles Of DIstributed Systems (OPODIS), Springer, 2008, pp. 184-196

DOI

Employing WS-BPEL Design Patterns for Grid Service Orchestration using a Standard WS-BPEL Engine and a Grid Middleware

A. Brinkmann, S. Gudenkauf, W. Hasselbring, A. Höing, H. Karl, O. Kao, H. Nitsche, G. Scherp, in: Proc. Cracow Grid Workshop (CGW), 2008, pp. 103-110


Enhancing SLA Provisioning by Utilizing Profit-Oriented Fault Tolerance

D. Battré, M. Hovestadt, O. Kao, A. Keller, K. Voss, in: Proc. Int. Conf. on Parallel and Distributed Computing and Systems (PDCS), 2008, pp. 212-218


EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks

M. Woehrle, C. Plessl, R. Lim, J. Beutel, L. Thiele, in: IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC), IEEE Computer Society, 2008, pp. 201-208

DOI

Germany, Belgium, France, and Back Again: Job Migration using Globus

D. Battré, M. Hovestadt, O. Kao, A. Keller, K. Voss, in: Proc. Int. Conf. on Grid Computing and Applications (GCA), 2008


GPU-Supported Image Compression for Remote Visualization - Realization and Benchmarking

S. Lietsch, P. Hermann Lensing, in: Proc. Int. Symp. on Visual Computing (ISVC), Springer, 2008, pp. 658-668

DOI

Guarantee and Penalty Clauses for Service Level Agreements

D. Battré, G. Birkenheuer, V. Deora, M. Hovestadt, O. Rana, O. Wäldrich, in: Proc. Cracow Grid Workshop (CGW), 2008, pp. 213-220


Guiding exploration by combining individual learning and imitation in societies of autonomous robots

W. Richert, F. Klompmaker, O. Niehörster, in: Proc. IFIP Conf. on Biologically Inspired Cooperative Computing (BICC), Springer, 2008, pp. 233-244

DOI

IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers

T. Schumacher, C. Plessl, M. Platzner, in: Many-core and Reconfigurable Supercomputing Conference (MRSC), 2008


Implementation of Virtual Execution Environments for improving SLA-compliant Job Migration in Grids

D. Battré, M. Hovestadt, O. Kao, A. Keller, K. Voss, in: Proc. Int. Workshop on Scheduling and Resource Management for Parallel and Distributed Systems, 2008

DOI
Abstract

Abstract: Commercial Grid users demand for contractually fixed QoS levels. Service Level Agreements (SLAs) are powerful instruments for describing such contracts. SLA-aware resource management is the foundation for realizing SLA contracts within the Grid. OpenCCS is such an SLA-aware RMS, using transparent checkpointing to cope with resource outages. It generates a compatibility profile for each checkpoint dataset, so that the job can be resumed even on resources within the Grid. However, only a small number of Grid resources comply to such a profile. This paper describes the concept of virtual execution environments and how they increase the number of potential migration targets.The paper also describes how these virtual execution environments have been implemented within the OpenCCS resource management system.


Implementing WS-Agreement in a Globus Toolkit 4.0 Environment

D. Battré, O. Kao, K. Voss, in: Proc. Usage of Service Level Agreements in Grids Workshop held in conjunction with International Conference on Grid Computing, Springer, 2008, pp. 409-418

DOI

Increasing Fault-tolerance by Introducing Virtual Execution Environments.

D. Battré, M. Hovestadt, O. Kao, A. Keller, K. Voss, 2008


Job Migration and Fault Tolerance in SLA-aware Resource Management Systems

D. Battré, M. Hovestadt, O. Kao, A. Keller, K. Voss, in: Proc. Int. Conf. on Grid and Pervasive Computing (GPC), 2008, pp. 43-48

DOI
Abstract

Contractually fixed service quality levels are mandatory prerequisites for attracting the commercial user to Grid environments. Service Level Agreements (SLAs) are powerful instruments for describing obligations and expectations in such a business relationship. At the level of local resource management systems, checkpointing and restart is an important instrument for realizing fault tolerance and SLA awareness. This paper highlights the concepts of migrating such checkpoint datasets to achieve the goal of SLA compliant job execution.


Layered understanding for sporadic imitation in a multi-robot scenario

W. Richert, O. Niehörster, M. Koch, in: Proc. IEEE/RSJ Int.Conf. on Intelligent Robots and Systems (IROS), IEEE, 2008

DOI

Overbooking in Planning Based Scheduling Systems

G. Birkenheuer, M. Hovestadt, O. Kao, K. Voß, in: Proc. Int. Conf. on Grid Computing & Applications (GCA), CSREA Press, 2008, pp. 242-248


Paderborn, Belgien, Frankreich und zurück

M. Hovestadt, A. Keller, K. Voss. Paderborn, Belgien, Frankreich und zurück. 2008.


Proc. Int. Workshop on Storage Network Architecture and Parallel I/Os (SNAPI)

A. Brinkmann, R. Chamberlain, IEEE Computer Society, 2008


Proceedings of the 1. GI/ITG KuVS Fachgespräch Virtualisierung

A. Brinkmann, H. Karl, Paderborn Center for Parallel Computing, Paderborn University, 2008


Quality Assurance of Grid Service Provisioning by Risk Aware Managing of Resource Failures

D. Battré, M. Hovestadt, O. Kao, A. Keller, K. Voss, in: Proc. Int. Conf. on Risks and Security of Internet and Systems, 2008


Recursive Evaluation of Fault Tolerance Mechanisms for SLA Management

K. Voss, in: Proc. Int. Conf. on Networking and Services (ICNS), IEEE, 2008, pp. 223-229

DOI

Redundant Data Placement Strategies for Cluster Storage Environments

A. Brinkmann, S. Effert, in: Proc. Int. Conf. on Principles Of DIstributed Systems (OPODIS), Springer, 2008, pp. 551-554

DOI

SelfS – A Real-Time Protocol for Virtual Ring Topologies

B. Griese, A. Brinkmann, M. Porrmann, in: Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS), IEEE, 2008, pp. 1-8

DOI

Storage Cluster Architectures

A. Brinkmann, S. Effert, in: Proc. of the GI/ITG KuVS Fachgespr ̈ach Virtualisierung, 2008, pp. 107-115


The GOmputer: Accelerating GO with FPGAs

M. Platzner, S. Döhre, M. Happe, T. Kenter, U. Lorenz, T. Schumacher, A. Send, A. Warkentin, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245-251


Virtual Execution Environments and the Negotiation of Service Level Agreements in Grid Systems

D. Battré, M. Hovestadt, O. Kao, A. Keller, K. Voss, in: Proc. Int. DMTF Academic Alliance Workshop on Systems and Virtualization Management: Standards and New Technologies, 2008

DOI
Abstract

Service Level Agreements (SLAs) have focal importance if the commercial customer should be attracted to the Grid. An SLA-aware resource management system has already been realize, able to fulfill the SLA of jobs even in the case of resource failures. For this, it is able to migrate checkpointed jobs over the Grid. At this, virtual execution environments allow to increase the number of potential migration targets significantly. In this paper we outline the concept of such virtual execution environments and focus on the SLA negotiation aspects.


Virtual Execution Environments for ensuring SLA-compliant Job Migration in Grids

D. Battré, M. Hovestadt, O. Kao, A. Keller, K. Voss, in: Proc. Int. Conf. on Services Computing (SCC), 2008

DOI
Abstract

OpenCCS is an SLA-aware resource management system which uses transparent checkpointing of applications and migration of checkpoint datasets for ensuring SLA-compliance also in case of resource outages. Migration of checkpoints presumes a high grade of compatibility between source and target resource. Hence, even in large Grid systems only a small number of resources are eligible migration targets. This short paper describes the concept of virtual execution environments and how they increase the number of potential migration targets. It will also outline an implementation within OpenCCS.


Virtual Supercomputer for HPC and HTC

G. Birkenheuer, A. Brinkmann, H. Dömer, S. Effert, C. Konersmann, O. Niehörster, J. Simon, in: Proc. Gemeinsamer Workshop der GI/ITG Fachgruppen "Betriebssysteme" und "KuVS": Virtualized IT infrastructures and their management, Leibniz-Rechenzentrum, 2008, pp. 37-49


2007

A CUDA-Supported Approach to Remote Rendering

S. Lietsch, O. Marquardt, in: Proc. Int. Symp. on Visual Computing (ISVC), Springer, 2007, pp. 724-733


AssessGrid, Economic Issues Underlying Risk Awareness in Grids

K. Voss, K. Djemame, I. Gourlay, J. Padgett, in: Proc. Int. Worksh. on Grid Economics and Business Models (GECON), Springer, 2007, pp. 170-175

DOI

Automated Wireless Sensor Network Testing

J. Beutel, M. Dyer, R. Lim, C. Plessl, M. Woehrle, M. Yuecel, L. Thiele, in: Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, 2007, pp. 303-303

DOI

Comparing Fault Tolerance Mechanisms for Self-Organizing Resource Management in Grids

K. Voss, in: Proc. Int. Conf. on Semantics, Knowledge and Grid (SKG), IEEE Computer Society, 2007, pp. 50-55

DOI

Computational Steering of Interactive and Distributed Virtual Reality Applications

S. Lietsch, H. Zabel, J. Berssenbruegge, in: Proc. ASME Computers and Information in Engineering Conference (CIE), ASME, 2007


Enhance Self-managing Grids by Risk Management

K. Voss, in: Proc. Int. Conf. on Networking and Services (ICNS), IEEE Computer Society, 2007, pp. 27-32

DOI

Gaining Users' Trust by Publishing Failure Probabilities

D. Battré, K. Djemame, O. Kao, K. Voss, in: Proc. Int. Conf. on Security and Privacy in Communications Networks (SecureComm), IEEE, 2007, pp. 193-198

DOI

Gather and Prepare Monitoring Data for Estimating Resource Stability

G. Birkenheuer, P. Majlender, H. Nitsche, K. Voss, E. Weber, in: Proc. Cracow Grid Workshop (CGW), 2007


Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework

M. Woehrle, C. Plessl, J. Beutel, L. Thiele, in: Proc. Workshop on Embedded Networked Sensors (EmNets), ACM, 2007, pp. 93-97

DOI


Planning-based Scheduling for SLA-awareness and Grid Integration

D. Battré, M. Hovestadt, O. Kao, A. Keller, K. Voss, in: Proc. Workshop of the UK PLANNING AND SCHEDULING Special Interest Group (PlanSIG), 2007

Abstract

Service level agreements (SLAs) are powerful instruments for describing all obligations and expectations in a business relationship. It is of focal importance for deploying Grid technology to commercial applications. The EC-funded project HPC4U (Highly Predictable Clusters for Internet Grids) aimed at introducing SLA-awareness in local resource management systems, while the EC-funded project AssessGrid introduced the notion of risk, which is associated with every business contract. This paper highlights the concept of planning based resource management and describes the SLA-aware scheduler developed and used in these projects.


Transparent Cross Border Migration of Parallel Multi Node Applications

D. Battré, M. Hovestadt, O. Kao, A. Keller, K. Voss, in: Proc. Cracow Grid Workshop, Academic Computer Center CYFRNET, 2007, pp. 334-341


Verteilte Berechnung und Darstellung automobiler Scheinwerfer

J. Berssenbrügge, S. Lietsch, in: Proc. Worksh. Augmented & Virtual Reality in der Produktentstehung, Heinz Nixdorf Institut, 2007, pp. 67-80


2006

First Steps of a Monitoring Framework to Empower Risk Assessment on Grids

N. Lerch, H. Nitsche, K. Voss, M. Hovestadt, in: Proc. Cracow Grid Workshop (CGW), 2006, pp. 216-223


Introducing Risk Management into the Grid

K. Djemame, I. Gourlay, J. Padgett, G. Birkenheuer, M. Hovestadt, O. Kao, K. Voss, in: Proc. Int. Conf. on e-Science and Grid Computing, IEEE Computer Society, 2006, pp. 28

DOI

Light Simulation in a Distributed Driving Simulator

S. Lietsch, H. Zabel, J. Berssenbruegge, V. Wittenberg, M. Eikermann, in: Proc. Int. Symp. on Visual Computing (ISVC), Springer, 2006, pp. 343-353

DOI

On Similarities of Grid Resources for Identifying Potential Migration Targets

G. Birkenheuer, S. Döhre, M. Hovestadt, O. Kao, K. Voss, in: Proc. Cracow Grid Workshop (CGW), 2006


Provision of Fault Tolerance with Grid-enabled and SLA-aware Resource Management Systems

F. Heine, M. Hovestadt, O. Kao, A. Keller, in: Parallel Computing: Current and Future Issues of High End Computing, 2006, pp. 113-120


Reformulating XPath queries and XSLT queries on XSLT views

S. Groppe, S. Böttcher, G. Birkenheuer, A. Höing, Data & Knowledge Engineering (2006), pp. 64-110

DOI

Risk Aware Migrations for Prepossessing SLAs

K. Voss, in: Proc. Int. Conf. on Networking and Services (ICNS), IEEE Computer Society, 2006, pp. 68

DOI

The First Step of Introducing Risk Management for Prepossessing SLAs

M. Hovestadt, O. Kao, K. Voss, in: Proc. Int. Conf. on Services Computing (SCC), IEEE Computer Society, 2006, pp. 36-43

DOI

The Virtual Resource Manager: Local Autonomy versus QoS Guarantees for Grid Applications

L. Burchard, F. Heine, H. Heiss, M. Hovestadt, O. Kao, A. Keller, B. Linnert, J. Schneider, in: Future Generation Grids, 2006, pp. 83-98

DOI
Abstract

In this paper, we describe the architecture of the virtual resource manager VRM, a management system designed to reside on top of local resource management systems for cluster computers and other kinds of resources. The most important feature of the VRM is its capability to handle quality-of-service (QoS) guarantees and service-level agreements (SLAs). The particular emphasis of the paper is on the various opportunities to deal with local autonomy for resource management systems not supporting SLAs. As local administrators may not want to hand over complete control to the Grid management, it is necessary to define strategies that deal with this issue. Local autonomy should be retained as much as possible while providing reliability and QoS guarantees for Grid applications, e.g., specified as SLAs.


Using WS-Agreement for Risk Management in the Grid

G. Birkenheuer, K. Djemame, I. Gourlay, O. Kao, J. Padgett, K. Voß, in: Proc. WS-Agreement Workshop (Open Grid Forum 18), 2006


2005

A Quality-of-Service Architecture for Future Grid Computing Applications.

L. Burchard, F. Heine, M. Hovestadt, O. Kao, A. Keller, B. Linnert, in: Proc. IEEE Int. Parallel & Distributed Processing Symposium (IPDPS), 2005, pp. 132a-132a

DOI
Abstract

The next generation grid applications demand grid middleware for a flexible negotiation mechanism supporting various ways of quality-of-service (QoS) guarantees. In this context, a QoS guarantee covers simultaneous allocations of various kinds of different resources, such as processor runtime, storage capacity, or network bandwidth, which are specified in the form of service level agreements (SLA). Currently, a gap exists between the capabilities of grid middleware and the underlying resource management systems concerning their support for QoS and SLA negotiation. In this paper we present an approach which closes this gap. Introducing the architecture of the virtual resource manager, we highlight its main QoS management features like run-time responsibility, co-allocation, and fault tolerance.


CoLoS - A System for Device Unaware and Position Dependent Communication Based on the Session Initiation Protocol

S. Lietsch, O. Kao, in: Proc. Intelligence in Communication Systems (INTELLCOMM), Springer, 2005, pp. 261-271

DOI

PIRANHA – Hunter of Idle Resources

G. Birkenheuer, W. Hagelweide, B. Hagemeier, V. Japs, M. Keller, N. Mayr, J. Meyer, T. Schumacher, K. Voß, M. Zajac, in: Proc. GI Informatiktage, Gesellschaft für Informatik (GI), 2005, pp. 91-94


SLA-aware Job Migration in Grid Environments

F. Heine, M. Hovestadt, O. Kao, A. Keller, in: Grid Computing: New Frontiers of High Performance Computing, 2005, pp. 185-201

DOI
Abstract

Grid Computing promises an efficient sharing of world-wide distributed resources, ranging from hardware, software, expert knowledge to special I/O devices. However, although the main Grid mechanisms are already developed or are currently addressed by tremendous research effort, the Grid environment still suffers from a low acceptance in different user communities. Beside difficulties regarding an intuitive and comfortable resource access, various problems related to the reliability and the Quality-of-Service while using the Grid exist. Users should be able to rely, that their jobs will have certain priority at the remote Grid site and that they will be finished upon the agreed time regardless of any provider problems. Therefore, QoS issues have to be considered in the Grid middleware but also in the local resource management systems at the Grid sites. However, most of the currently used resource management systems are not suitable for SLAs, as they do not support resource reservation and do not offer mechanisms for job checkpointing/migration respectively. The latter are mandatory for Grid providers as rescue anchor in case of system failures or system overload. This paper focuses on SLA-aware job migration and presents a work, which is being performed in the EU supported project HPC4U.


2004

An Architecture for SLA-aware Resource Management

L. Burchard, H. Heiss, M. Hovestadt, O. Kao, A. Keller, B. Linnert, in: Proceedings of the GI-Meeting on Operating Systems, 2004


Efficient Querying of Transformed XML Documents

S. Groppe, S. Böttcher, G. Birkenheuer, in: Proc. Int. Conf. on Enterprise Information Systems (ICEIS), 2004, pp. 241-250


SLA-aware Job Migration in Grid Environments

O. Kao, M. Hovestadt, A. Keller, in: Proc. Advanced Research Workshop on High Perfomance Computing: Technology and Applications, 2004


Using XSLT Stylesheets to Transform XPath Queries

S. Groppe, S. Böttcher, R. Heckel, G. Birkenheuer, in: Proc. East-European Conf. on Advances in Databases and Information Systems (ADBIS), 2004


Virtual Resource Manager: An Architecture for SLA-aware Resource Management

L. Burchard, M. Hovestadt, O. Kao, A. Keller, B. Linnert, in: Proc. Int. Symposium on Cluster Computing and the Grid (CCGRID), 2004

DOI
Abstract

The next generation Grid will demand the Grid middleware to provide flexibility, transparency, and reliability. This implies the appliance of service level agreements to guarantee a negotiated level of quality of service. These requirements also affect the local resource management systems providing resources for the Grid. At this a gap between these demands and the features of today's resource management systems becomes apparent. In this paper we present an approach which closes this gap. Introducing the architecture of the virtual resource manager we highlight its main features of runtime responsibility, resource virtualization, information hiding, autonomy provision, and smooth integration of existing resource management system installations.


2003

Scheduling in HPC Resource Management Systems: Queuing vs. Planning

M. Hovestadt, O. Kao, A. Keller, A. Streit, in: Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), 2003, pp. 1-20

DOI
Abstract

Nearly all existing HPC systems are operated by resource management systems based on the queuing approach. With the increasing acceptance of grid middleware like Globus, new requirements for the underlying local resource management systems arise. Features like advanced reservation or quality of service are needed to implement high level functions like co-allocation. However it is difficult to realize these features with a resource management system based on the queuing concept since it considers only the present resource usage. In this paper we present an approach which closes this gap. By assigning start times to each resource request, a complete schedule is planned. Advanced reservations are now easily possible. Based on this planning approach functions like diffuse requests, automatic duration extension, or service level agreements are described. We think they are useful to increase the usability, acceptance and performance of HPC machines. In the second part of this paper we present a planning based resource management system which already covers some of the mentioned features.


2002

Performance Evaluation, Analysis and Optimization

B. P. Miller, J. Labarta, F. Schintke, J. Simon, in: Proc. European Conf. on Parallel Processing (Euro-Par), Springer, 2002, pp. 131

DOI

2001

A Cache Simulator for Shared Memory Systems

F. Schintke, J. Simon, A. Reinefeld, in: Proc. Int. Conf. on Computational Science (ICCS), Springer, 2001, pp. 569-578

DOI

Anatomy of a Resource Management System for HPC Clusters

A. Keller, A. Reinefeld, Annual Review of Scalable Computing (2001), pp. 1-31

DOI
Abstract

Workstation clusters are often not only used for high-throughput computing in time-sharing mode but also for running complex parallel jobs in space-sharing mode. This poses several difficulties to the resource management system, which must be able to reserve computing resources for exclusive use and also to determine an optimal process mapping for a given system topology. On the basis of our CCS software, we describe the anatomy of a modern resource management system. Like Codine, Condor, and LSF, CCS provides mechanisms for the user-friendly system access and management of clusters. But unlike them, CCS is targeted at the effective support of space-sharing parallel computers and even metacomputers. Among other features, CCS provides a versatile resource description facility, topology-based process mapping, pluggable schedulers, and hooks to metacomputer management.


Early Experiences with the EGrid Testbed

J. Gehring, A. Keller, A. Reinefeld, A. Streit, in: Proc. Int. Symposium on Cluster Computing and the Grid (CCGRID), 2001, pp. 130-137

DOI
Abstract

The Testbed and Applications working group of the European Grid Forum (EGrid) is actively building and experimenting with a grid infrastructure connecting several research-based supercomputing sites located in Europe. The paper reports on our first feasibility study: running a self-migrating version of the Cactus simulation code across the European grid testbed, including "live" remote data visualization and steering from different demonstration booths at Supercomputing 2000, in Dallas, TX. We report on the problems that had to be resolved for this endeavour and identify open research challenges for building production-grade grid environments.


Efficient Resource Management for Malleable Applications

J. Hungershöfer, A. Streit, J. Wierum, Paderborn Center for Parallel Computing, 2001


Lessons Learned While Operating Two Large SCI Clusters

A. Keller, A. Krawinkel, in: Proc. Int. Symposium on Cluster Computing and the Grid (CCGRID), 2001, pp. 303-310

DOI
Abstract

The availability of commodity high performance components for workstations and networks made it possible to build up large, PC based compute clusters at modest costs. These clusters seem to be a realistic alternative to proprietary, massively parallel systems with respect to the price/performance ratio. However, from the administration point of view, those systems are still often solely a collection of autonomous nodes, connected by a fast short area network. Therefore, aiming at providing the best possible performance in daily work to all users, a lot of work has to be done before obtaining the expected result. The paper describes the problem areas we had to cope with during the integration of two large SCI clusters (one with 64 and one with 192 processors) in the environment of the Paderborn Center for Parallel Computing.


2000

RsdEditor: A Graphical User Interface for Specifying Metacomputer Components

R. Baraglia, A. Keller, D. Laforenza, A. Reinefeld, in: Proc. Heterogenous Computing Workshop HCW at IPDPS, 2000, pp. 336-348

DOI
Abstract

RsdEditor is a graphical user interface which produces specifications of computational resources. It is used in the RSD (Resource and Service Description) environment for specifying, registering, requesting and accessing resources and services in a metacomputer. RsdEditor was designed to be used by the administrators and users of metacomputing environments. At the administrator level, the GUI is used to describe the available computing and networking components of a metacomputer. At the user level, RsdEditor can be used to specify which characteristics of the computational resources are needed to execute a meta-application. This paper is organized as follows: it first introduces RsdEditor. It then briefly describes the RSD environment, and finally, it highlights various features and implementation issues of RsdEditor.



1999

A Resource Description Environment for Distributed Computing Systems

M. Brune, A. Reinefeld, J. Varnholt, in: Proc. Int. Symp. High-Performance Distributed Computing (HPDC), IEEE Computer Society, 1999


Large-Scale SCI Clusters in Practice: Architecture and Performance in SCI

J. Simon, A. Reinefeld, O. Heinz, in: SCI: Scalable Coherent Interface. Architecture and Software for High-Performance Compute Clusters, Springer, 1999, pp. 367-381

DOI

Managing Clusters of Geographically Distributed High-Performance Computers

M. Brune, J. Gehring, A. Keller, A. Reinefeld, Concurrency, Practice, and Experience (1999), pp. 887-911

DOI
Abstract

We present a software system for the management of geographically distributed high‐performance computers. It consists of three components: 1. The Computing Center Software (CCS) is a vendor‐independent resource management software for local HPC systems. It controls the mapping and scheduling of interactive and batch jobs on massively parallel systems; 2. The Resource and Service Description (RSD) is used by CCS for specifying and mapping hardware and software components of (meta‐)computing environments. It has a graphical user interface, a textual representation and an object‐oriented API; 3. The Service Coordination Layer (SCL) co‐ordinates the co‐operative use of resources in autonomous computing sites. It negotiates between the applications' requirements and the available system services.


Multi-User System Management on SCI Cluster

M. Brune, A. Keller, A. Reinefeld, in: SCI - Scalable Coherent Interface: Architecture and Software for High Performance Compute Clusters, 1999, pp. 443-460

DOI
Abstract

The growing maturity of hardware and software components has tempted researchers to build very large SCI clusters with several hundred processors that are operated as high-performance compute servers in multi-user mode. In this chapter, we present a resource management software for the user access and system administration of high-performance compute clusters named Computing Center Software (CCS). It is in day-to-day use since 1992 on various parallel systems and has recently been adapted to the management of SCI clusters. CCS provides pluggable schedulers, optimal space partitioning for multiple users, reliable user access, and powerful tools for specifying resources and services by means of a specification language and a graphical user interface. After a brief introduction in the remainder of this section, we describe the CCS system architecture and the characteristics of its resource description facilities.


Resource Management for High-Performance PC Clusters

M. Brune, A. Keller, A. Reinefeld, in: Proc. Int. Conf. on High-Performance Computing and Networking (HPCN), 1999, pp. 270-280

DOI
Abstract

With the recent availability of cost-effective network cards for the PCI bus, researchers have been tempted to build up large compute clusters with standard PCs. Many of them are operated with workstation cluster management software in high-throughput or single user mode. For very large clusters with more than 100 PEs, however, it becomes necessary to implement a full fledged resource management software that allows to partition the system for multi-user access. In this paper, we present our Computing Center Software (CCS), which was originally designed for managing massively parallel high-performance computers, and now adapted to modern workstation clusters. It provides - partitioning of exclusive and non-exclusive resources, - hardware-independent scheduling of interactive and batch jobs, - open, extensible interfaces to other resource management systems, - a high degree of reliability.


Specifying Resources and Services in Metacomputing Systems

M. Brune, J. Gehring, A. Keller, A. Reinefeld, in: High-Performance Cluster Computing: Architecture and Systems, 1999, pp. 186-200

DOI
Abstract

With a steadily increasing number of services, metacomputing is now gaining importance in science and industry. Virtual organizations, autonomous agents, mobile computing services, and high-performance client–server applications are among the many examples of metacomputing services. For all of them, resource description plays a major role in organizing access, use, and administration of the computing components and software services. We present a generic Resource and Service Description (RSD) for specifying the hardware and software components of (meta-) computing environments. Its graphical interface allows metacomputer users to specify their resource requests. Its textual counterpart gives service providers the necessary flexibility to specify topology and properties of the available system and software resources. Finally, its internal object-oriented representation is used to link different resource management systems and service tools. With these three representations, our generic RSD approach is a key component for building metacomputer environments.


1998

CCS Resource Management in Networked HPC Systems

A. Keller, A. Reinefeld, in: Proc. Heterogenous Computing Workshop (HCW) at IPPS, 1998, pp. 44-56

DOI
Abstract

CCS is a resource management system for parallel high-performance computers. At the user level, CCS provides vendor-independent access to parallel systems. At the system administrator level, CCS offers tools for controlling (i.e, specifying, configuring and scheduling) the system components that are operated in a computing center. Hence the name "Computing Center Software". CCS provides: hardware-independent scheduling of interactive and batch jobs; partitioning of exclusive and non-exclusive resources; open, extensible interfaces to other resource management systems; a high degree of reliability (e.g. automatic restart of crashed daemons); fault tolerance in the case of network breakdowns. The authors describe CCS as one important component for the access, job distribution, and administration of networked HPC systems in a metacomputing environment.


RSD - Resource and Service Description

M. Brune, J. Gehring, A. Keller, A. Reinefeld, in: Proc. Int. Conf. on High-Performance Computing Systems (HPCS), 1998

DOI
Abstract

RSD (Resource and Service Description) is a scheme for specifying resources and services in complex heterogeneous computing systems and metacomputing environments. At the system administrator level, RSD is used to specify the available system components, such as the number of nodes, their interconnection topology, CPU speeds, and available software packages. At the user level, a GUI provides a comfortable, high-level interface for specifying system requests. A textual editor can be used for defining repetitive and recursive structures. This gives service providers the necessary flexibility for fine-grained specification of system topologies, interconnection networks, system and software dependent properties. All these representations are mapped onto a single, coherent internal object-oriented resource representation. Dynamic aspects (like network performance, availability of compute nodes, and compute node loads) are traced at runtime and included in the resource description to allow for optimal process mapping and dynamic task load balancing at runtime at the metacomputer level. This is done in a self-organizing way, with human system operators becoming only involved when new hardware/software components are installed.


Specifying Resources and Services in Metacomputing Environments

M. Brune, J. Gehring, A. Keller, B. Monien, Parallel Computing (1998), pp. 1751-1776

DOI
Abstract

With a steadily increasing number of services, metacomputing is now gaining importance in science and industry. Virtual organizations, autonomous agents, mobile computing services, and high-performance client–server applications are among the many examples of metacomputing services. For all of them, resource description plays a major role in organizing access, use, and administration of the computing components and software services. We present a generic Resource and Service Description (RSD) for specifying the hardware and software components of (meta-) computing environments. Its graphical interface allows metacomputer users to specify their resource requests. Its textual counterpart gives service providers the necessary flexibility to specify topology and properties of the available system and software resources. Finally, its internal object-oriented representation is used to link different resource management systems and service tools. With these three representations, our generic RSD approach is a key component for building metacomputer environments.


The Latency-of-Data-Access model for Analyzing Parallel Computation

J. Simon, J. Wierum, Information Processing Letters - Special Issue on Models of Computation (1998), pp. 255-261

DOI

1997

A Closer Step towards Management of Metacomputing-Resources

M. Brune, C. Hellmann, A. Keller, in: Proc. Workshop Hypercomputing at ITG/GI-Conference Architekur von Rechensystemen, 1997


Embedding SCI into PVM

M. Fischer, J. Simon, in: Proc. European Parallel Virtual Machine / Message Passing Interface Users’ Group Meeting (EuroPVM/MPI), Springer, 1997, pp. 175-184

DOI

Experiences with a SCI Multiprocessor Workstation Cluster

O. Heinz, J. Simon, in: Proc. Int. Conf. on Architecture of Computing Systems (ARCS), VDE Verlag, 1997


SCI multiprocessor PC cluster in a WindowsNT environment

J. Simon, O. Heinz, in: Proc. Workshops im Rahmen der 14. ITG/GI-Fachtagung Architektur von Rechensystemen, 1997, pp. 189-199


The MOL Project: An Open, Extensible Metacomputer

A. Reinefeld, R. Baraglia, T. Decker, J. Gehring, D. Laforenza, F. Ramme, T. Römke, J. Simon, in: Proc. Heterogenous Computing Workshop (HCW), IEEE Computer Society, 1997, pp. 17-31

DOI

Workload Analysis of Computation Intensive Tasks: Case Study on SPEC CPU95 Benchmarks

J. Simon, R. Weicker, M. Vieth, in: Proc. European Conf. on Parallel Processing (Euro-Par), Springer, 1997, pp. 971-984

DOI

1996

Accurate Performance Prediction for Massively Parallel Systems and its Applications

J. Simon, J. Wierum, in: Proc. European Conf. on Parallel Processing (Euro-Par), Springer, 1996, pp. 675-688

DOI

On Accurate Performance Prediction for Massively Parallel Systems and its Applications

J. Simon, J. Wierum, Paderborn Center for Parallel Computing, 1996


Performance Prediction of Benchmark Programs for Massively Parallel Architectures

J. Simon, J. Wierum, in: Proc. Annual Int. Conf. on High-Performance Computers (HPCS), 1996


Sequential Performance versus Scalability: Optimizing Parallel LU-Decomposition

J. Simon, J. Wierum, in: Proc. Int. Conf. on High-Performance Computing and Networking (HPCN-Europe), Springer, 1996, pp. 627-632

DOI

1995

An Efficient Mapping Library for Parix

T. Römke, M. Röttger, U. Schroeder, J. Simon, in: Proc. ZEUS Workshop on Par. Programming and Computation, IOS Press, 1995


Implementation of a Parallel and Distributed Mapping Kernel for PARIX

M. Röttger, U. Schroeder, J. Simon, in: Proc. Int. Conf. on High-Performance Computing and Networking, Springer, 1995, pp. 781-786

DOI

On Efficient Embeddings of Grids into Grids in PARIX

T. Römke, M. Röttger, U. Schroeder, J. Simon, in: Proc. European Conf. on Parallel Processing (Euro-Par), Springer, 1995, pp. 179-192

DOI

Parallel CG Poisson Solver for PowerPC 601

S. Blazy, U. Dralle, J. Simon, in: PowerXplorer User Report - Applications and Projects on the Parsytec PowerXplorer Parallel Computer, Heinrich-Heine-Universität, 1995


SparcStation SCI-Interface

J. Gehring, J. Simon, Paderborn Center for Parallel Computing, 1995


1994

Leistung eines Parallelrechners auf Basis des PowerPC-Prozessors

J. Simon, in: Parallele Datenverarbeitung aktuell: TAT '94, IOS Press, 1994, pp. 38-45


1993

Benutzung virtueller Topologien unter PARIX

J. Simon, Paderborn Center for Parallel Computing, 1993


Problem Independent Distributed Simulated Annealing and its Applications

R. Diekmann, R. Lüling, J. Simon, Paderborn Center for Parallel Computing, 1993


Problem Independent Distributed Simulated Annealing and its Applications

R. Diekmann, J. Simon, in: Applied Simulated Annealing, Springer, 1993, pp. 17-44

DOI

Virtual Topology Library for PARIX

M. Röttger, J. Simon, U. Schroeder, Paderborn Center for Parallel Computing, 1993


1992

A General Purpose Distributed Implementation of Simulated Annealing

R. Diekmann, R. Lüling, J. Simon, in: Proc. 13th IMACS World Congress on Computation and Applied Mathematics, 1992


A General Purpose Distributed Implementation of Simulated Annealing

R. Diekmann, R. Lüling, J. Simon, in: Proc. IEEE Symp. on Parallel and Distributed Processing (SPDP), IEEE, 1992, pp. 94-101

DOI

Implementierung von Simulated Annealing auf Transputer-Systemen

R. Diekmann, R. Lüling, B. Monien, J. Simon, in: Parallele Datenverarbeitung mit dem Transputer, Springer, 1992, pp. 361-368

DOI

Leistungssteigerung paralleler Systeme durch virtuelle Topologien

R. Diekmann, J. Simon, in: Abstraktband des 4. bundesweiten Transputer-Anwender-Treffens (TAT 92), 1992


Open list in Research Information System

The University for the Information Society