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Data Center Building O Show image information

Data Center Building O

Training: Productive Design for Intel FPGAs – Combining HLS with lower-level Tools

On Mai 20, 2019, we will offer a full day training on developing FPGA accelerators in cooperation with Intel. The training will provide an overview of Intel's product portfolio and programming models for designing FPGA accelerators. Special emphasis will be given on programming models to complement the high productivity OpenCL-based design flow. This includes highly optimized components from more specialized design generators (DSP Builder, Intel HLS) or lower-level tools (RTL) and sheds light on the Intel Acceleration Stack. The training will also feature hands-on exercises on remote systems.


  • Previous experience with FPGAs (intermediate level)
  • Own Laptop with working wifi setup for hands-on exercises via webex over browser

Preliminary Agenda

  • FPGA Programming Models that can be Combined with OpenCL Designs
    • RTL
    • HLS
    • DSP Builder
  • Pracical Lab with HLS
  • Introduction to Intel Acceleration Stack
  • Discussion: Combining OpenCL with RTL/DSP Builder Components
  • Discussion: Intel FPGA Curriculum and University Program
  • Conclusions, Q&A


The event is limited to 20 attendees.

Attendance is free of charge. 

If you are interested in attending, please send email to Tobias Kenter using the subject [intel-fpga-training] Registration request.

The registration is now closed.

Location and Time

The event wil take place at the Paderborn Center for Parallel Computing at the Paderborn University Campus Warburger Strasse.

Date: May 20, 2019
Time: 10:00-17:30
Room: O2.267
Address: Pohlweg 51, 33098 Paderborn

About the trainer

The course will be taugth in English by Bill Jenkins (Intel).



Dr. Tobias Kenter

Paderborn Center for Parallel Computing (PC2)

Scientific Advisor FPGA Acceleration

+49 5251 60-4340
+49 5251 60-1714

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