FPGA Training: Working with OpenCL for Intel FPGAs
On September 24-25 2018, a 2-day training about FPGA design with OpenCL for Intel FPGAs will be held at the Paderborn Center for Parallel Computing. The training complements the installation of 32 Stratix 10 FPGAs in the Noctua project for HPC users that consider porting part of their application to custom accelerator designs. It will combine general concepts of OpenCL for FPGAs with hands-on exercises.
Attendance is limited to 15 persons.
Agenda
Heterogeneous Parallel Computing
OpenCL Platform and Host-side Software
- OpenCL overview
- PlatformLayerAPI
- RuntimeLayerAPI
Executing OpenCL Kernels
- Writing kernels
- Launching kernels
NDRange Kernels
- Kernels and work-item hierarchy
- Memorymodel
OpenCL on Intel FPGAs
- The Intel FPGA SDK for OpenCL
- DebugTools
- FPGA-specificfeatures
Single-Work Item Kernels
- Introduction
- Understanding execution models and optimization reports
- Resolving common dependency issues
- Good design practices
- Advanced uses
- Application examples
Optimizing Local Memory
- Allocating Local Memory
- Local Memory Access Synchronization
- Banking and Coalescing
- Limitations
- LocalMemoryReports