Meet us at ISC 2017

We are participating at ISC 2017 in Frankfurt, which is the largest European conference and trade show on High-Performance Computing. You can meet us on Wednesday in the exhibition hall at the HiPEAC booth (A-1430) from 10:00-13:30 and at the Gauss-Allianz boot from 16:00-18:00.

Our presentations this year, center around the topic of Heterogeneous and FPGA-Accelerated Computing:

Approximate Computing – A Suitable Paradigm for Scientific Computing?

Approximate Computing (AC) is an emerging computing paradigm that compromises the exactness of the computation for improved performance or energy efficiency. While AC has already attracted attention for domains that are inherently resilient to approximations (e.g. processing of audio and video or machine learning) the potential in scientific computing is so far not well understood. In our current research, we study, which numerical methods can profit from AC techniques if accuracy bounds are desirable or needed.

Can OpenCL Compilers make FPGAs Accessible for HPC?

Numerous case studies have demonstrated that FPGA can provide substantial performance and efficiency benefits to computationally challenging applications.  Recently, FPGAs technology and tools have made significant strides towards improved floating-point capabilities and high-level programming toolflows, which makes the technology accessible for a wider range of developers. In this presentation, we report on our ongoing work of accelerating a finite difference solver for Maxwell’s equations using an OpenCL-based FPGA toolflow.

Automatic and Transparent Acceleration of Applications

Because of the stagnation of single-thread performance and the move towards accelerators, legacy applications do no longer see a performance increase when executed on the latest computing systems. If codes are expected to be used for a long time and have a large user base, code modernization, i.e. porting the code to modern programming languages and libraries with parallelism support, is likely worth the effort. For legacy codes, manual modernization may not be economical. In our work, we study just-in-time compilation approaches that automatically adapt these codes to use GPU and FPGA accelerators without any manual intervention.

Accelerating and Parallelizing Tree-Search for Crypto-Attacks with FPGAs

FPGAs are most efficient for regular, throughput computing on data streams. Hence, the acceleration of tree search problems with FPGAs is typically not regarded as particularly promising. In this work on accelerating so-called “cold boot” crypto attacks, we have proven this common knowledge wrong. We have demonstrated that FPGAs are beneficial for solving certain hard tree search problems and that we can also successfully apply a work stealing strategy to parallelize the hardware implementation. Finally, we show that it even makes sense to fully customized FPGA accelerators that tailored to the problem instance not only the problem class.


Prof. Dr. Christian Plessl

Dr. Tobias Kenter

Dr. Jens Simon


Dr. Tobias Kenter

Paderborn Center for Parallel Computing (PC2)

Fachberater FPGA Beschleunigung

E-Mail schreiben +49 5251 60-4340
business-card image

Dr. Jens Simon

Paderborn Center for Parallel Computing (PC2)

Leiter HPC-Betrieb

E-Mail schreiben +49 5251 60-1731