Sie haben Javascript deaktiviert!
Sie haben versucht eine Funktion zu nutzen, die nur mit Javascript möglich ist. Um sämtliche Funktionalitäten unserer Internetseite zu nutzen, aktivieren Sie bitte Javascript in Ihrem Browser.

Info-Icon Diese Seite ist nicht in Deutsch verfügbar

Data Center Building O Bildinformationen anzeigen

Data Center Building O

| Paderborn Center for Parallel Computing

Tutorial on Working with OpenCL for Intel FPGAs

On September 24 ­­­­­­– 25 2018, a tutorial on Working with OpenCL for Intel FPGAs was held at the Paderborn Center for Parallel Computing. With the new supercomputer Noctua that was inaugurated on September 21, the PC² has installed 32 state of the art FPGAs (Field Programmable Gate Arrays) as particularly energy efficient accelerators. With a focus on current users of the Paderborn HPC (high-performance computing) systems with little or no experience in FPGA programming, the training extends the base of developers that can write customized application code for the FPGAs.

The tutorial was conducted by Wolfgang Loewer of the FPGA Consulting company El Camino. Founded by former Altera employees in 1999, El Camino specialized from the beginning on engineering, training and consulting for FPGAs and CPLDs manufactured by Altera, now Intel FPGA. While most industrial customers still focus on FPGA designs specified with hardware description languages (HDL), new high-level synthesis design flows, in particular based on OpenCL have increasingly raised interest over the last couple of years.

On the first day of the tutorial, general concepts of OpenCL were introduced, along with a special emphasis on pipeline parallelism as the key to efficient execution on FPGAs. The second day covered advanced optimization techniques including making best use of the flexible layout of local memory resources within the FPGA. The presentation of concepts and examples was complemented with hands-on exercises that allowed the 16 participants to apply the new knowledge in practice.


Dr. Tobias Kenter

Paderborn Center for Parallel Computing (PC2)

Fachberater FPGA Beschleunigung

Zur Person

Die Universität der Informationsgesellschaft