HARP Cluster
After a beta testing phase with selected participants, the HARP cluster was opened on August 18, 2017 to a broad community of researchers within the Intel Hardware Accelerator Research Program (HARP). At peak times, the HARP cluster had several hundred registered users and executed tens of thousands of jobs per month. After several years of operation, the service has been terminated.
Further links
- Press release
- Technical documentation wiki (only for registered users)
- Discussion group for the Hardware Accelerator Research Program (moderated by Intel)
Technical description
| System | Xeon+FPGA |
| Processors | 14-core Broadwell CPU |
| FPGAs | Arria 10 GX 1150 |
| Main Memory | 64 GiB per node, shared memory hierarchy between CPU and FPGA |
| Partitions per development stack |
|
| Workload manager | Slurm |
Selected Publications using the HARP-Cluster
Transparent Control Flow Transfer between CPU and Accelerators for HPC
D. Granhão, J.C. Canas Ferreira, Electronics (2021).
OpenCL-based FPGA Accelerator for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors
D. Castells-Rufas, S. Marco-Sola, Q. Aguado-Puig, A. Espinosa-Morales, J.C. Moure, L. Alvarez, M. Moreto, in: 2021 31st International Conference on Field-Programmable Logic and Applications (FPL), IEEE, 2021.
Exploration of FPGA-Based Hardware Designs for QR Decomposition for Solving Stiff ODE Numerical Methods Using the HARP Hybrid Architecture
C. Alberto Oliveira de Souza Junior, J. Bispo, J.M.P. Cardoso, P.C. Diniz, E. Marques, Electronics (2020).
Combining Multiple Optimized FPGA-based Pulsar Search Modules Using OpenCL
H. Wang, P. Thiagaraj, O. Sinnen, Journal of Astronomical Instrumentation (2019).
Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL
T. Faict, E.H. D’Hollander, B. Goossens, Algorithms (2019).
Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform
A. Rodríguez, A. Navarro, R. Asenjo, F. Corbera, R. Gran, D. Suárez, J. Nunez-Yanez, The Journal of Supercomputing (2019).
Energy Efficient Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip Package
M.A. Souza, L.A. Maciel, P.H. Penna, H.C. Freitas, in: 2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2019.
Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators
L. Sommer, J. Oppermann, A. Molina, C. Binnig, K. Kersting, A. Koch, in: 2018 IEEE 36th International Conference on Computer Design (ICCD), 2019.
Constructing Concurrent Data Structures on FPGA with Channels
H. Yan, Z. Li, L. Liu, S. Yin, S. Wei, in: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019.
FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory
Z. Li, L. Liu, Y. Deng, J. Wang, Z. Liu, S. Yin, S. Wei, in: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019.
Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution
Z. Li, L. Liu, Y. Deng, S. Yin, S. Wei, IEEE Computer Architecture Letters (2018) 147–150.
Automatic Offloading of Cluster Accelerators
C. Ceissler, R. Nepomuceno, M. Pereira, G. Araujo, in: 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2018.
A Case Study in Using OpenCL on FPGAs: Creating an Open-Source Accelerator of the AutoDock Molecular Docking Software
Show all publications
L. Solis-Vasquez, A. Koch, in: FSP Workshop 2018; Fifth International Workshop on FPGAs for Software Programmers, 2018, pp. 1–10.