From September 4 to 7, 2023, the Paderborn Center for Parallel Computing (PC2) hosted their first hackathon event that brought together researchers with diverse scientific backgrounds to collaborate on innovative High-Performance Computing (HPC) projects. Key themes included software development, accelerator programming, performance engineering, and project infrastructure support.
This event exemplified the power of collaborative innovation in the world of High-Performance Computing. Participants and advisors worked together to overcome challenges and achieve remarkable results in just four days.
Diverse Projects, Unique Challenges
Multithreading Performance Improvements in Peridynamics.jl:
Addressing multithreading challenges in the Peridynamics.jl package, this project improved performance by mitigating issues like false sharing and inefficient thread assignment. The result was a boost in overall efficiency.
Optimizing MKL Thread Usage for Improved Performance in Julia:
This project centered on optimizing core usage when working with multi-threaded Math Kernel Library (MKL). The team found that fine-tuning core utilization and using Slurm Arrays instead of automatic multi-threaded MKL led to significant performance improvements.
Implementing the Wilson Dslash operator and its inverse in SIMULATeQCD:
This team achieved a major milestone by implementing the Wilson Dslash operator and its inverse in the SIMULATeQCD codebase. This enhancement is vital for lattice Quantum Chromodynamics (QCD) simulations, with potential applications in comprehending phenomena like shear and bulk viscosities of the Quark-Gluon-Plasma.
Quantum Optimization with Photonic Quantum Computers:
This project focused on solving optimization problems with continuous variables. The emphasis was on implementing cost Hamiltonians with universal gate sets and decomposing them into gate sequences - an essential step in quantum optimization.
FPGA Acceleration of Breadth-First Search Algorithm:
In this project, the team focused on optimizing the Breadth-First Search (BFS) algorithm for FPGA acceleration. Their efforts included streamlining the code build process, identifying bottlenecks, and achieving a notable average performance increase of 1.25x.
Moving from software based to FPGA accellerated RTL simulation:
This project marked a transition from software-based RTL simulation to FPGA-accelerated RTL simulation using FireSim. The team achieved significant speedups, reducing simulation times considerably and enhancing the efficiency of their work.
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