On March 25 2019, Tobias Kenter conducted a tutorial at the DATE 2019 conference in Florence under the title OpenCL design flows for Intel and Xilinx FPGAs - common optimization strategies, design patterns and vendor-specific differences. Featuring tools for both Intel and Xilinx FPGAs, this tutorial provides the community with practical guidance based on the experience in OpenCL based FPGA acceleration at PC².
While the DATE website only allowed on-side access to the tutorial material for registered participants, we have now made the slide deck available on our website along with the repository of sample codes and generated reports. For further details refer to this page.
